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ORCIDAntonio Pelella
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2010 – 2019
- 2012
[j1]James D. Warnock, Yiu-Hing Chan, Sean M. Carey, Huajun Wen, Patrick J. Meaney, Guenter Gerwig, Howard H. Smith, Yuen H. Chan, John Davis, Paul Bunce, Antonio Pelella, Daniel Rodko, Pradip Patel, Thomas Strach, Doug Malone, Frank Malgioglio, José Neves, David L. Rude, William V. Huott:
Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. IEEE J. Solid State Circuits 47(1): 151-163 (2012)- 2011
- [c5]Antonio Pelella, Yuen H. Chan, Bargav Balakrishnan, Pradip Patel, Daniel Rodko, Richard E. Serton:
Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor. ISSCC 2011: 72-73
2000 – 2009
- 2006
- [c4]John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr:
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. ISSCC 2006: 2564-2571 - 2005
- [c3]Antonio Pelella, Arthur Tuminaro, Ryan T. Freese, Yuen H. Chan:
A 8Kb domino read SRAM with hit logic and parity checker. ESSCIRC 2005: 359-362
1990 – 1999
- 1999
- [c2]William V. Huott, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Dennis Manzer, Pia N. Sanda, Steven C. Wilson, Yuen H. Chan, Antonio Pelella, Stanislav Polonsky:
The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA). ITC 1999: 883-891 - 1993
- [c1]William R. Reohr, Yuen H. Chan, Donald W. Plass, Antonio Pelella, Philip T. Wu:
Design SRAMs for burn-in. VTS 1993: 164-170
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