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"A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor."

John Davis et al. (2006)

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DOI: 10.1109/ISSCC.2006.1696322

access: closed

type: Conference or Workshop Paper

metadata version: 2020-06-09

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  - conf/isscc/DavisPBCPJCHKPL06
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  - https://dblp.org/rec/conf/isscc/DavisPBCPJCHKPL06
John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr:
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. ISSCC 2006: 2564-2571

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