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ORCID25th ISQED 2024: San Francisco, CA, USA
- 25th International Symposium on Quality Electronic Design, ISQED 2024, San Francisco, CA, USA, April 3-5, 2024. IEEE 2024, ISBN 979-8-3503-0927-0
- Surajit Das, Hetang Patel, Chandan Karfa, Kartheek Bellamkonda, Rahul Reddy, Disha Puri, Anshul Jain, Arijit Sur, Pradip Prajapati:
RTL Simulation Acceleration with Machine Learning Models. 1-7 - Kamrul Hasan, Sara Tehranipoor, Nima Karimian, Surbhi Vasudeva:
NAND Flash-Based Digital Fingerprinting for Robust and Secure Hardware Authentication. 1-6 - Alexander Coyle, Hui Jiang, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal:
Dual Use Circuitry for Early Failure Warning and Test. 1-8 - Qirui Zhang
, Mehdi Saligane, Hun-Seok Kim, David T. Blaauw, Georgios Tzimpragos, Dennis Sylvester:
Quantum Circuit Simulation with Fast Tensor Decision Diagram. 1-8 - X. Zhou, W. Yang, Siau Ben Chiah:
Composite Sub-surface Model for RF GaN-HEMTs. 1 - Sanket Shukla, Sai Manoj Pudukotai Dinakarrao:
Bring it On: Kinetic Energy Harvesting to Spark Machine Learning Computations in IoTs. 1-6 - Teo Vallone, Hayri Verner Hasou, Ernesto Colizzi, Sara Vinco, Davide Zoni:
A novel virtual prototyping methodology for timing-accurate simulation of AMS circuits. 1-8 - Najmeh Nazari, Furi Xiang, Chongzhou Fang, Hosein Mohammadi Makrani, Aditya Puri, Kartik Patwari, Hossein Sayadi, Setareh Rafatirad, Chen-Nee Chuah, Houman Homayoun:
LLM-FIN: Large Language Models Fingerprinting Attack on Edge Devices. 1-6 - Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik:
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. 1-8 - Jialin Liu, Han Wang:
Model Extraction Attack against On-device Deep Learning with Power Side Channel. 1-5 - Pratik Shrestha, Ioannis Savidis:
EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation. 1-7 - Hansika Weerasena, Prabhat Mishra:
Lightweight Multicast Authentication in NoC-based SoCs. 1-8 - Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi:
A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS. 1-5 - Miguel Angel Alfaro Zapata, Amirhossein Shahshahani, Zeljko Zilic:
Automated Assertion Checker Generator and Information Flow Tracking for Security Verification. 1-6 - Shamik Kundu, Arnab Raha, Deepak A. Mathaikutty, Kanad Basu:
RASH: Reliable Deep Learning Acceleration using Sparsity-based Hardware. 1 - Zhengyao Gu, Diego Troy Lopez, Lilas Alrahis, Ozgur Sinanoglu:
Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNs. 1-8 - Dongning Ma, Cong Hao, Xun Jiao:
Hyperdimensional Computing vs. Neural Networks: Comparing Architecture and Learning Process. 1-5 - Xingyu Meng, Abhrajit Sengupta, Kanad Basu:
A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans. 1-8 - Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo, Ishan G. Thakkar:
A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators. 1-8 - Prakash Dhungana, Sayed Ahmad Salehi:
RTKWS: Real-Time Keyword Spotting Based on Integer Arithmetic for Edge Deployment. 1-7 - Florian Freye, Jie Lou, Christian Lanius, Tobias Gemmeke:
Merits of Time-Domain Computing for VMM - A Quantitative Comparison. 1-8 - Endri Kaja, Nicolas Gerlin, Bihan Zhao, Daniela Sanchez Lopera, Jad Al Halabi, Azam Sher Khan, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods. 1-8 - Rahul Sreekumar, Minseong Park, Mohammad Nazmus Sakib, Bhupendra S. Reniwal, Kyusang Lee, Mircea R. Stan:
EASI-CiM: Event-driven Asynchronous Stream-based Image classifier with Compute-in-Memory kernels. 1-8 - Sayed Ahmad Salehi, Prakash Dhungana:
A Low-cost keyword spotting architecture based on wavelet packets feature extraction for edge device. 1 - Anh-Tuan Hoang, Mark Kennaway, Dung Tuan Pham, Thai Son Mai, Ayesha Khalid, Ciara Rafferty, Máire O'Neill:
Deep Learning Enhanced Side Channel Analysis on CRYSTALS-Kyber. 1-8 - Simon Toni Hofmann, Marcel Walter, Lorenzo Servadei, Robert Wille:
Thinking Outside the Clock: Physical Design for Field-coupled Nanocomputing with Deep Reinforcement Learning. 1-8 - Shamik Kundu, Navnil Choudhury, Kanad Basu:
QuEST: Quantum Circuit Output Estimation using Gaussian Distribution Analysis. 1-8 - Jieyu Lin, Sai Qian Zhang, Alberto Leon-Garcia:
sLLM: Accelerating LLM Inference using Semantic Load Balancing with Shared Memory Data Structures. 1-6 - Mohammad Khairul Bashar, Zheyu Li, Vijaykrishnan Narayanan, Nikhil Shukla:
An FPGA-based Max-K-Cut Accelerator Exploiting Oscillator Synchronization Model. 1-8 - Prashanth H. C., Madhav Rao:
Roofline Performance Analysis of DNN Architectures on CPU and GPU Systems. 1-8 - Subrata Das, Swaroop Ghosh:
Trojan Attacks on Variational Quantum Circuits and Countermeasures. 1-8 - Czea Sie Chuah, Alexander Hepp, Christian Appold, Tim Leinmüller:
Trojan Assets and Attack Vectors in Processors. 1-10 - Rohit Kumar Gupta, Chiranjeev Grover, Etienne Maurin, Jean-Arnaud Francois, Olivier Minez, Sébastien Marchal:
Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF. 1-5 - Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu:
Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network. 1-8 - Mason Conkel, Wen Zhang, Chen Pan:
Enhancing Self-sustaining IoT Systems with Autonomous and Smart UAV Data Ferry. 1-7 - Sahidul Islam, Seth Klupka, Ramin Mohammadi, Yu-Fang Jin, Mimi Xie:
Deep Learning Based IoT System for Real-time Traffic Risk Notifications. 1-6 - Subhradip Chakraborty, Dinesh Kushwaha, Abhishek Goel, Anmol Singla, Anand Bulusu, Sudeb Dasgupta:
An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network. 1-6 - Hossein Sayadi, Zhangying He, Hosein Mohammadi Makrani, Houman Homayoun:
Intelligent Malware Detection based on Hardware Performance Counters: A Comprehensive Survey. 1-10 - Joong-Won Jeon, Andrew B. Kahng, Jaehyun Kang, Jaehwan Kim, Mingyu Woo:
SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-Optimization. 1-8 - Seongbin Kwon, Dohun Kim, Sunghye Park, Seojeong Kim, Seokhyeong Kang:
QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization. 1-7 - Zhengfeng Wu, Ioannis Savidis:
Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling. 1-7 - Md. Mazharul Islam, Md. Shafayat Hossain, Ahmedullah Aziz:
A SPICE-based Emulator Framework for Quantum Error Correction Circuits using LC Resonators. 1-5 - Steven Colleman, Arne Symons, Victor J. B. Jung, Marian Verhelst:
Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms. 1-6 - Chin-Wei Wu, Yu-Min Lee, Pei-Yu Huang, Bo-Jiun Yang, Tai-Yu Chen, Ting-Chang Huang, Yen-Lin Lee:
SpotLight: A Hotspot-Greedy, Light-Weighted, and Automated Thermal Modeling Framework for Early Smartphone Design. 1-8 - Bipul Boro, Rushik Parmar, Ashvinikumar Dongre, Gaurav Trivedi:
Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing. 1-8 - Po-Chun Wang, Kai-Jie Ton, Rung-Bin Lin:
Routing Intent Aware Pin Access Point Selection for Standard Cell Designs. 1-8 - Dantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao:
Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators. 1-8 - Srinivasa Rao Maram, Subrahmanyam Boyapati, Vijay Shankar Pasupureddi:
A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS Technology. 1-7 - Ali Imangholi, Mona Hashemi, Amirabbas Momeni, Siamak Mohammadi, Trevor E. Carlson:
FAST-GO: Fast, Accurate, and Scalable Hardware Trojan Detection using Graph Convolutional Networks. 1-8 - B. N. Tejas, Rakshit Bhatia, Madhav Rao:
HISPE: High-Speed Configurable Floating-Point Multi-Precision Processing Element. 1-8 - Lokesh Maji, Aman Prajapati, Madhav Rao:
Design and Evaluation of Parametric NTT Hardware Unit using different Multiplier based Modular Reduction Techniques. 1-6 - B. S. Ajay, Phani Pavan K, Madhav Rao:
DESPINE: NAS generated Deep Evolutionary Adaptive Spiking Network for Low Power Edge Computing Applications. 1-8 - Koustubh Phalak, Swaroop Ghosh:
Non-parametric Greedy Optimization of Parametric Quantum Circuits. 1-7 - Hasita Veluri, Dilip Vasudevan:
BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array Architecture. 1-9 - Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu:
Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology. 1-8 - Khalil Sedki, Yang Cindy Yi:
Advancing Analog Reservoir Computing through Temporal Attention and MLP Integration. 1-8 - Sai Qian Zhang, Jieyu Lin, Qi Zhang, Yu-Jia Chen:
Learning Client Selection Strategy for Federated Learning across Heterogeneous Mobile Devices. 1-7 - Gopal Raut, Pranose J. Edavoor, David Selvakumar, Ritambhara Thakur:
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators. 1-8 - Christos P. Sotiriou, George Rafael Goudroumanis, Nikolaos Sketopoulos, Christos Georgakidis:
Swarm - A VLSI Timing, Fanout-aware Clustering Algorithm. 1-8 - Md. Shohidul Islam, Ihsen Alouani, Khaled N. Khasawneh:
Hardware Support for Trustworthy Machine Learning: A Survey. 1-6 - Yinghua Hu, Kaixin Yang, Subhajit Dutta Chowdhury, Pierluigi Nuzzo:
DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks. 1-8 - Kshitij Raj, Aritra Bhattacharyay, Swarup Bhunia, Sandip Ray:
Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats. 1 - Mousam Hossain, Muhtasim Alam Chowdhury, Ronald F. DeMara, Soheil Salehi:
Sensitivity Analysis of SOT-MTJs to Manufacturing Process Variation: A Hardware Security Perspective. 1-5 - Rouwaida Kanj, Jamil Kawa:
A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and Beyond. 1-8 - Krithika Dhananjay, Vasilis F. Pavlidis, Ayse K. Coskun, Emre Salman:
Enhanced Detection of Thermal Covert Channel Attacks in Multicore Processors. 1-7 - Abdullah Sahruri, Martin Margala, Ugur Çilingiroglu:
HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With an Offset-Compensated Comparator. 1-7 - Hafsah Shahzad, Ahmed Sanaullah, Sanjay Arora, Ulrich Drepper, Martin C. Herbordt:
AutoAnnotate: Reinforcement Learning based Code Annotation for High Level Synthesis. 1-9 - Dantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao:
PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN. 1-8 - Junghyun Yoon, Heechun Park:
Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations. 1-7 - N. S. Aswathy, Hemangee K. Kapoor:
Write Intensity based Foresightful Page Migration for Hybrid memories. 1-8 - Suryansh Upadhyay, Swaroop Ghosh:
Obfuscating Quantum Hybrid-Classical Algorithms for Security and Privacy. 1-8 - Zhengyang Ye, Zhisheng Chen, Youlin Pan, Genggeng Liu, Wenzhong Guo, Tsung-Yi Ho, Xing Huang:
Timing-Driven High-Level Synthesis for Continuous-Flow Microfluidic Biochips. 1-6 - Shan Shen, Zhiqiang Liu, Wenjian Yu:
SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits. 1-7 - Yibo Liu, Sheldon X.-D. Tan:
GridVAE: Fast Power Grid EM-Aware IR Drop Prediction and Fixing Accelerated by Variational AutoEncoder. 1-6 - Mahati Basavaraju, Vinay Rayapati, Madhav Rao:
Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating Formats. 1-8 - Mahdi Hasanzadeh, Meisam Abdollahi, Amirali Baniasadi, Ahmad Patooghy:
Thermo-Attack Resiliency: Addressing a New Vulnerability in Opto-Electrical Network-on-Chips. 1-9 - Shiya Liu, Yang Yi:
Unleashing Energy-Efficiency: Neural Architecture Search without Training for Spiking Neural Networks on Loihi Chip. 1-7 - Bindu G. Gowda, Prashanth H. C., V. N. Muralidhara, Madhav Rao:
Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach. 1-8 - Kusum Lata, Prashant Singh, Sandeep Saini:
Exploring Model Poisoning Attack to Convolutional Neural Network Based Brain Tumor Detection Systems. 1-7 - Siqin Liu, Avinash Karanth:
SCORCH: Neural Architecture Search and Hardware Accelerator Co-design with Reinforcement Learning. 1-8 - Dho Ui Lim, Heechun Park:
Graph Neural Network-Based Detailed Placement Optimization Framework. 1-6 - Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Oluwaseun Adewunmi Alo, Jeffrey Todd Hastings, Justin Scott Woods:
A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics. 1-8 - Jiayi Wang, Songyu Sun, Xunzhao Yin:
Single-Ferroelectric FET based Associative Memory for Data-Intensive Pattern Matching. 1-7 - Akash Levy, Joe Walston, Sourav Samanta, Priyanka Raina, Stelios Diamantidis:
FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization. 1-8 - Zeinab Soueidan, Rouwaida Kanj:
nvXNOR Design with Enhanced Store Capability for BNN Applications. 1-7 - Stavros Simoglou, Iordanis Lilitsis, Nikolaos Blias, Christos P. Sotiriou:
Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model. 1-8 - Zhengyang Chen, Yuhan Zhu, Zhen Chen, Zhisheng Chen, Genggeng Liu:
High-Level Synthesis for Microfluidic Biochips Considering Actual Volume Management and Channel Storage. 1-8 - Ron Jokai, Cheng Tan, Jeff Jun Zhang:
Fused Functional Units for Area-Efficient CGRAs. 1-8 - Amir Alipour-Fanid, Monireh Dabaghchian, Long Jiao, Kai Zeng:
Learning-Based Secure Spectrum Sharing for Intelligent IoT Networks. 1-8 - Quentin Forcioli, Sumanta Chaudhuri, Jean-Luc Danger:
TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments. 1-8 - Rupshali Roy, Subrata Das, Swaroop Ghosh:
Hardware Trojans in Quantum Circuits, Their Impacts, and Defense. 1-8 - Ping Li, Zhong Guan:
Parasitic Capacitance Patterns Grid Density Binarization and Shifted Reflection Step Sequence Encoding for Dimensionality Reduction. 1-8 - Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. 1-8 - Alejandro Almeida, Muneeba Asif, Md. Tauhidur Rahman, Mohammad Ashiqur Rahman:
Side-Channel-Driven Intrusion Detection System for Mission Critical Unmanned Aerial Vehicles. 1-9 - Joseph Clark, Himanshu Thapliyal:
Peephole Optimization for Quantum Approximate Synthesis. 1-8 - Zhenyi Gao, Sheqin Dong, Zifei Cheng, Wenjian Yu:
MORE-Router+: Multilayer Multi-capacity ORdered Escape Routing via Bus-oriented Layer Assignment. 1-7 - Haimanti Chakraborty, Ranga Vemuri:
RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation. 1-8 - Soramichi Akiyama, Ryota Shioya, Yuto Miyatake, Tongxin Yang:
Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives. 1-9 - Cedric Feghali, Farid N. Najm:
Fast Current Constraints Generation for Chip Safety. 1-8 - Daniela Sanchez Lopera, Robert Kunzelmann, Endri Kaja, Wolfgang Ecker:
Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs. 1-8 - Capucine Mien Verone Berger-Sigrist, Andrea Guerrieri:
Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography. 1 - Chadi Jabbour:
A multi band flexible N-path filter suited for non-contiguous channel aggregation. 1-6 - Behnam Ghavami, Amin Kamjoo, Lesley Shannon, Steve Wilton:
DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization. 1-7 - Philipp Fengler, Sani R. Nassif, Ulf Schlichtmann:
Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes. 1-8 - Maliha Tasnim, Chinmay Raje, Sheldon X.-D. Tan:
Multi-ALM: Run-time Multi-Level Reconfigurable Approximate Logarithmic Multiplier. 1-6 - Sheng Lu, Liuting Shang, Sungyong Jung, Chenyun Pan:
Emerging Reconfigurable Logic Device Based FPGA Design and Optimization. 1-8 - Kang Jun Bai, Hao Jiang, Zhuwei Qin, Clare Thiem:
Temporal-encoded 6T-RRAM with Bidirectional Control for Future Neuromorphic Systems. 1-6
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last updated on 2024-12-02 21:35 CET by the dblp team
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