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2020 – today
- 2024
[c9]Endri Kaja, Nicolas Gerlin, Jad Al Halabi, Ares Tahiraga, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs. DFT 2024: 1-4- [c8]Endri Kaja, Nicolas Gerlin, Ares Tahiraga, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V. DFT 2024: 1-6 - [c7]Endri Kaja, Nicolas Gerlin, Bihan Zhao, Daniela Sanchez Lopera, Jad Al Halabi, Azam Sher Khan, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods. ISQED 2024: 1-8 - 2023
- [c6]Nicolas Gerlin, Endri Kaja, Fabian Vargas, Li Lu, Anselm Breitenreiter
, Junchao Chen, Markus Ulbricht, Maribel Gomez, Ares Tahiraga, Sebastian Prebeck, Eyck Jentzsch, Milos Krstic, Wolfgang Ecker:
Bits, Flips and RISCs. DDECS 2023: 140-149 - [c5]Endri Kaja, Nicolas Gerlin, Robert Kunzelmann, Keerthikumara Devarajegowda, Wolfgang Ecker:
Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation. MCSoC 2023: 508-515 - 2022
- [c4]Endri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
MetaFS: Model-driven Fault Simulation Framework. DFT 2022: 1-4 - [c3]Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. VLSI-SoC 2022: 1-6 - [c2]Endri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation. VLSI-SoC 2022: 1-6 - [i1]Endri Kaja, Nicolas Gerlin, Luis Rivas, Monideep Bora, Keerthikumara Devarajegowda, Wolfgang Ecker:
MetFI: Model-driven Fault Simulation Framework. CoRR abs/2204.13183 (2022) - 2021
- [c1]Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker:
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models. DFT 2021: 1-6
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