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2020 – today
- 2024
[j14]Chris Keilbart
, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon:
Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors. ACM Trans. Reconfigurable Technol. Syst. 17(2): 33:1-33:32 (2024)- [c56]Behnam Ghavami, Mani Sadati, Mohammad Shahidzadeh, Lesley Shannon, Steve Wilton:
A Semi Black-Box Adversarial Bit- Flip Attack with Limited DNN Model Information. ICCD 2024: 96-104 - [c55]Behnam Ghavami, Mohammad Shahidzadeh, Lesley Shannon, Steve Wilton:
ZOBNN: Zero-Overhead Dependable Design of Binary Neural Networks with Deliberately Quantized Parameters. IOLTS 2024: 1-7 - [c54]Behnam Ghavami, Amin Kamjoo, Lesley Shannon, Steve Wilton:
DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization. ISQED 2024: 1-7 - [c53]Behnam Ghavami, Mahdi Sajadi, Lesley Shannon, Steve Wilton:
Boosting Multiple Multipliers Packing on FPGA DSP Blocks via Truncation and Compensation-based Approximation. ISVLSI 2024: 222-227 - [i11]Behnam Ghavami, Amin Kamjoo, Lesley Shannon, Steve Wilton:
DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization. CoRR abs/2404.02947 (2024) - [i10]Behnam Ghavami, Mohammad Shahidzadeh, Lesley Shannon, Steve Wilton:
ZOBNN: Zero-Overhead Dependable Design of Binary Neural Networks with Deliberately Quantized Parameters. CoRR abs/2407.04964 (2024) - [i9]Mohammad Shahidzadeh, Behnam Ghavami, Steve Wilton, Lesley Shannon:
Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting. CoRR abs/2411.15442 (2024) - [i8]Behnam Ghavami, Mani Sadati, Mohammad Shahidzadeh, Lesley Shannon, Steve Wilton:
A Semi Black-Box Adversarial Bit-Flip Attack with Limited DNN Model Information. CoRR abs/2412.09450 (2024) - 2023
- [c52]Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon:
Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors. FCCM 2023: 202 - [i7]Behnam Ghavami, Lesley Shannon:
Unraveling the Integration of Deep Machine Learning in FPGA CAD Flow: A Concise Survey and Future Insights. CoRR abs/2303.10508 (2023) - [i6]Eduardo Rhod, Behnam Ghavami, Zhenman Fang, Lesley Shannon:
A Cycle-Accurate Soft Error Vulnerability Analysis Framework for FPGA-based Designs. CoRR abs/2303.12269 (2023) - 2022
- [j13]Lesley Shannon:
Introduction to Special Section on FPGA 2020. ACM Trans. Reconfigurable Technol. Syst. 15(1): 1:1-1:2 (2022) - [j12]Eric Matthews, Alec Lu, Zhenman Fang, Lesley Shannon:
Quick-Div: Rethinking Integer Divider Design for FPGA-based Soft-processors. ACM Trans. Reconfigurable Technol. Syst. 15(3): 32:1-32:27 (2022) - [j11]Alec Lu, Zhenman Fang, Lesley Shannon:
Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking. ACM Trans. Reconfigurable Technol. Syst. 15(4): 43:1-43:33 (2022) - [c51]Behnam Ghavami, Mani Sadati, Zhenman Fang, Lesley Shannon:
FitAct: Error Resilient Deep Neural Networks via Fine-Grained Post-Trainable Activation Functions. DATE 2022: 1239-1244 - [c50]Behnam Ghavami, Mahdi Sajedi, Mohsen Raji, Zhenman Fang, Lesley Shannon:
A Majority-based Approximate Adder for FPGAs. DSD 2022: 53-59 - [c49]Behnam Ghavami, Mani Sadati, Mohammad Shahidzadeh, Zhenman Fang, Lesley Shannon:
Blind Data Adversarial Bit-flip Attack against Deep Neural Networks. DSD 2022: 899-904 - [c48]Behnam Ghavami, Seyd Movi, Zhenman Fang, Lesley Shannon:
Stealthy Attack on Algorithmic-Protected DNNs via Smart Bit Flipping. ISQED 2022: 1-7 - 2021
- [j10]Maya B. Gokhale, Lesley Shannon:
FPGA Computing. IEEE Micro 41(4): 6-7 (2021) - [c47]Alec Lu, Zhenman Fang, Weihua Liu, Lesley Shannon:
Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers through Microbenchmarking. FPGA 2021: 105-115 - [c46]Behnam Ghavami, Seyed Milad Ebrahimi, Zhenman Fang, Lesley Shannon:
LEAP: A Deep Learning based Aging-Aware Architecture Exploration Framework for FPGAs. FPGA 2021: 146 - [c45]Behnam Ghavami, Milad Ibrahimipour, Zhenman Fang, Lesley Shannon:
MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework. FPL 2021: 369-373 - [e3]Lesley Shannon, Michael Adler:
FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28 - March 2, 2021. ACM 2021, ISBN 978-1-4503-8218-2 [contents] - [i5]Behnam Ghavami, Mani Sadati, Mohammad Shahidzadeh, Zhenman Fang, Lesley Shannon:
BDFA: A Blind Data Adversarial Bit-flip Attack on Deep Neural Networks. CoRR abs/2112.03477 (2021) - [i4]Kiarash Saremi, Hossein Pedram, Behnam Ghavami, Mohsen Raji, Zhenman Fang, Lesley Shannon:
SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs. CoRR abs/2112.04136 (2021) - [i3]Behnam Ghavami, Seyd Movi, Zhenman Fang, Lesley Shannon:
Stealthy Attack on Algorithmic-Protected DNNs via Smart Bit Flipping. CoRR abs/2112.13162 (2021) - [i2]Behnam Ghavami, Mani Sadati, Zhenman Fang, Lesley Shannon:
FitAct: Error Resilient Deep Neural Networks via Fine-Grained Post-Trainable Activation Functions. CoRR abs/2112.13544 (2021) - 2020
- [c44]Eric Matthews, Yuhui Gao, Lesley Shannon:
Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors. FCCM 2020: 120-128 - [c43]Seyed Milad Ebrahimipour, Behnam Ghavami, Hamid Mousavi, Mohsen Raji, Zhenman Fang, Lesley Shannon:
Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural Network. ICCAD 2020: 31:1-31:9 - [c42]Alec Lu, Zhenman Fang, Nazanin Farahpour, Lesley Shannon:
CHIP-KNN: A Configurable and High-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs. FPT 2020: 139-147 - [e2]Stephen Neuendorffer, Lesley Shannon:
FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, February 23-25, 2020. ACM 2020, ISBN 978-1-4503-7099-8 [contents]
2010 – 2019
- 2019
- [j9]Mohammad A. Usmani, Shahrzad Keshavarz, Eric Matthews, Lesley Shannon, Russell Tessier, Daniel E. Holcomb:
Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 364-375 (2019) - [c41]Eric Matthews, Alec Lu, Zhenman Fang, Lesley Shannon:
Rethinking Integer Divider Design for FPGA-Based Soft-Processors. FCCM 2019: 289-297 - [c40]Ameer M. S. Abdelhadi, Lesley Shannon:
Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online Arithmetic. FPT 2019: 383-386 - 2018
- [c39]Eric Matthews, Zavier Aguila, Lesley Shannon:
Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISA. FCCM 2018: 1-8 - [c38]Ameer M. S. Abdelhadi, Guy G. F. Lemieux, Lesley Shannon:
Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories. FPL 2018: 243-250 - 2017
- [c37]Nicholas C. Doyle, Eric Matthews, Graham M. Holland, Alexandra Fedorova, Lesley Shannon:
Performance impacts and limitations of hardware memory access trace collection. DATE 2017: 506-511 - [c36]Eric Matthews, Lesley Shannon:
TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features. FPL 2017: 1-4 - 2016
- [j8]Eric Matthews, Lesley Shannon, Alexandra Fedorova:
Shared Memory Multicore MicroBlaze System with SMP Linux Support. ACM Trans. Reconfigurable Technol. Syst. 9(4): 26:1-26:22 (2016) - [c35]Mohammad Reza Mohammadnia, Lesley Shannon:
A multi-beam Scan Mode Synthetic Aperture Radar processor suitable for satellite operation. ASAP 2016: 83-90 - [p1]Jeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton:
Systems-on-Chip on FPGAs. FPGAs for Software Programmers 2016: 261-283 - 2015
- [c34]Lesley Shannon, Veronica Cojocaru, Cong Nguyen Dao, Philip Heng Wai Leong:
Technology Scaling in FPGAs: Trends in Applications and Architectures. FCCM 2015: 1-8 - [c33]Eric Matthews, Nicholas C. Doyle, Lesley Shannon:
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems. FPGA 2015: 156-159 - [i1]Lesley Shannon, Eric Matthews, Nicholas C. Doyle, Alexandra Fedorova:
Performance monitoring for multicore embedded computing systems on FPGAs. CoRR abs/1508.07126 (2015) - 2014
- [c32]Farnaz Gharibian, Lesley Shannon, Peter Jamieson:
A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only). FPGA 2014: 242 - [c31]Farnaz Gharibian, Lesley Shannon, Peter Jamieson:
Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data. FPL 2014: 1-6 - 2013
- [j7]Farnaz Gharibian, Lesley Shannon, Peter Jamieson, Kevin Chung:
Analyzing System-Level Information's Correlation to FPGA Placement. ACM Trans. Reconfigurable Technol. Syst. 6(3): 15:1-15:21 (2013) - [c30]Peter Jamieson, Farnaz Gharibian, Lesley Shannon:
Supergenes in a genetic algorithm for heterogeneous FPGA placement. IEEE Congress on Evolutionary Computation 2013: 253-260 - 2012
- [j6]Cindy Mark, Scott Y. L. Chin, Lesley Shannon, Steven J. E. Wilton:
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation. ACM Trans. Embed. Comput. Syst. 11(S2): 42:1-42:25 (2012) - [j5]Lesley Shannon, Oliver Diessel, Neil W. Bergmann:
Guest Editorial: Field-Programmable Technology. J. Signal Process. Syst. 67(1): 1-2 (2012) - [c29]Michael Henrey, Sean Edmond, Lesley Shannon, Carlo Menon:
Bio-inspired walking: A FPGA multicore system for a legged robot. FPL 2012: 105-111 - [c28]Eric Matthews, Lesley Shannon, Alexandra Fedorova:
Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support. FPL 2012: 224-230 - [c27]Mohammad Reza Mohammadnia, Lesley Shannon:
Minimizing the error: A study of the implementation of an Integer Split-Radix FFT on an FPGA for medical imaging. FPT 2012: 360-367 - [c26]Snehasish Kumar, Hongzhou Zhao, Arrvindh Shriraman, Eric Matthews, Sandhya Dwarkadas, Lesley Shannon:
Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy. MICRO 2012: 376-388 - 2011
- [j4]Lesley Shannon, Paul Chow:
Leveraging reconfigurability in the hardware/software codesign process. ACM Trans. Reconfigurable Technol. Syst. 4(3): 28:1-28:27 (2011) - [c25]Lesley Shannon, Jian Li, Mohammad Reza Mohammadnia, Marinko Sarunic:
Evaluating the scalability of high-performance, Fourier-Domain Optical Coherence Tomography on GPGPUs and FPGAs. ACSCC 2011: 483-487 - [c24]Jian Li, Marinko Sarunic, Lesley Shannon:
Scalable, High Performance Fourier Domain Optical Coherence Tomography: Why FPGAs and Not GPGPUs. FCCM 2011: 49-56 - [c23]Aws Ismail, Lesley Shannon:
FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators. FCCM 2011: 170-177 - [c22]David Dickin, Lesley Shannon:
Exploring FPGA technology mapping for fracturable LUT minimization. FPT 2011: 1-8 - [c21]Edward Chen, Victor Gusev Lesau, Dorian Sabaz, Lesley Shannon, William A. Gruver:
FPGA Framework for Agent Systems Using Dynamic Partial Reconfiguration. HoloMAS 2011: 94-102 - 2010
- [j3]Edward Chen, William A. Gruver, Lesley Shannon, Dorian Sabaz:
EuTOPIA: Facilitating Processor-Based DPR Systems for non-DPR Experts. J. Next Gener. Inf. Technol. 1(1): 4-18 (2010) - [c20]Jian Li, David Dickin, Lesley Shannon:
Customizing controller instruction sets for application-specific architectures. ASAP 2010: 337-340 - [c19]Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon:
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research. FCCM 2010: 149-156 - [c18]Jason Lee, Lesley Shannon:
Predicting the performance of application-specific NoCs implemented on FPGAs. FPGA 2010: 23-32 - [c17]Farnaz Gharibian, Lesley Shannon, Peter Jamieson:
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement. FPL 2010: 544-549 - [c16]Eric Matthews, Lesley Shannon, Alexandra Fedorova:
A configurable framework for investigating workload execution. FPT 2010: 409-412
2000 – 2009
- 2009
- [e1]Neil W. Bergmann, Oliver Diessel, Lesley Shannon:
Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009. IEEE Computer Society 2009, ISBN 978-1-4244-4377-2 [contents] - 2008
- [c15]David Dickin, Lesley Shannon:
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms. ASAP 2008: 67-72 - [c14]Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary F. Margrave:
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator. ASAP 2008: 197-202 - [c13]Edward Chen, William A. Gruver, Dorian Sabaz, Lesley Shannon:
Facilitating Processor-Based DPR Systems for non-DPR Experts. FCCM 2008: 318-319 - [c12]Edward Chen, Dorian Sabaz, William A. Gruver, Lesley Shannon:
A new flexible PR domain model to replace the fixed multi-PR region model for DPR systems. FPT 2008: 257-260 - [c11]Wayne Chen, Lesley Shannon:
An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs. FPT 2008: 361-364 - 2007
- [j2]Lesley Shannon, Paul Chow:
SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 377-390 (2007) - [j1]Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow:
Routability of Network Topologies in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 948-951 (2007) - [c10]James Dykes, Paulman Chan, Glenn H. Chapman, Lesley Shannon:
A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGA. FPT 2007: 373-376 - 2006
- [c9]Manuel Saldaña, Lesley Shannon, Paul Chow:
The routability of multiprocessor network topologies in FPGAs. FPGA 2006: 232 - [c8]Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow:
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. FPL 2006: 1-6 - [c7]Manuel Saldaña, Lesley Shannon, Paul Chow:
The routability of multiprocessor network topologies in FPGAs. SLIP 2006: 49-56 - 2005
- [c6]Lesley Shannon, Paul Chow:
Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. FCCM 2005: 63-72 - [c5]Lesley Shannon, Paul Chow:
Leveraging Reconfigurability in the Design Process. FPL 2005: 731-732 - [c4]Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow:
Designing an FPGA SoC Using a Standardized IP Block Interface. FPT 2005: 341-342 - 2004
- [c3]Lesley Shannon, Paul Chow:
Using reconfigurability to achieve real-time profiling for hardware/software codesign. FPGA 2004: 190-199 - [c2]Lesley Shannon, Paul Chow:
Maximizing system performance: using reconfigurability to monitor system communications. FPT 2004: 231-238 - 2003
- [c1]Lesley Shannon, Paul Chow:
Standardizing the Performance Assessment of Reconfigurable Processor Architectures. FCCM 2003: 282-283
Coauthor Index
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