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ORCIDSebastian Huhn 0001
Person information
- affiliation: University of Bremen, Institute of Computer Science, Germany
Other persons with the same name
- Sebastian Huhn 0002 — Max Planck Institute for Human Cognitive and Brain Sciences, Department of Neurology, Leipzig, Germany
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2020 – today
- 2024
[c24]Payam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn, Rolf Drechsler:
A Multi-Objective Evolutionary Approach for Test Network Design. ETS 2024: 1-4- 2023
- [c23]Jens Trommer
, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, V. Sessi, M. Drescher, S. Kolodinski, M. Wiatr:
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. DATE 2023: 1-6 - [c22]Payam Habiby, Sebastian Huhn, Rolf Drechsler:
RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks. DFT 2023: 1-6 - [c21]Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler:
Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. ETS 2023: 1-6 - [c20]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods. ETS 2023: 1-6 - [c19]Daniel Tille, Leon Klimasch, Sebastian Huhn:
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin. VTS 2023: 1-6 - 2022
- [c18]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods. ETS 2022: 1-2 - [c17]Sebastian Huhn, Rolf Drechsler:
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques. ITC 2022: 609-618 - [c16]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection. VTS 2022: 1-7 - 2021
- [c15]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks. DFT 2021: 1-6 - [c14]Payam Habiby, Sebastian Huhn, Rolf Drechsler:
Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability. DTIS 2021: 1-4 - 2020
- [b1]Sebastian Huhn:
Next generation design for testability, debug and reliability using formal techniques. University of Bremen, Germany, 2020, pp. 1-170 - [c13]Payam Habiby, Sebastian Huhn, Rolf Drechsler:
Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains. DFT 2020: 1-6 - [c12]Rolf Drechsler, Sebastian Huhn, Christina Plump:
Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials. DSD 2020: 518-525
2010 – 2019
- 2019
- [j1]Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler:
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 875-887 (2019) - [c11]Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, Rolf Drechsler:
SAT-Hard: A Learning-Based Hardware SAT-Solver. DSD 2019: 74-81 - [c10]Sebastian Huhn, Daniel Tille, Rolf Drechsler:
Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns. ETS 2019: 1-2 - [c9]Sebastian Huhn, Daniel Tille, Rolf Drechsler:
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems. ITC-Asia 2019: 115-120 - 2018
- [c8]Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler:
SAT-Lancer: A Hardware SAT-Solver for Self-Verification. ACM Great Lakes Symposium on VLSI 2018: 479-482 - [c7]Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler:
Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems. LDIC 2018: 400-405 - 2017
- [c6]Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler:
Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. ASP-DAC 2017: 182-187 - [c5]Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler:
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. DATE 2017: 578-583 - [c4]Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler:
Reconfigurable TAP controllers with embedded compression for large test data volume. DFT 2017: 1-6 - [c3]Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler:
Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. SSCI 2017: 1-6 - 2016
- [c2]Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler:
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. ETS 2016: 1-6 - [c1]Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler:
Exploring superior structural materials using multi-objective optimization and formal techniques. ISED 2016: 13-17
Coauthor Index
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