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2020 – today
- 2022
[b1]Buse Ustaoglu:
Hardware packages for self-verification and secure partial reconfiguration / von Buse Ustaoğlu. University of Bremen, Germany, 2022, pp. 1-116
2010 – 2019
- 2019
- [c7]Kenneth Schmitz
, Buse Ustaoglu, Daniel Große, Rolf Drechsler:
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. ARC 2019: 112-126 - [c6]Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, Rolf Drechsler:
SAT-Hard: A Learning-Based Hardware SAT-Solver. DSD 2019: 74-81 - 2018
- [c5]Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler:
SAT-Lancer: A Hardware SAT-Solver for Self-Verification. ACM Great Lakes Symposium on VLSI 2018: 479-482 - 2016
- [c4]Buse Ustaoglu, Berna Örs Yalçin:
Reliability analysis of MIPS-32 microprocessor register files designed with different fault tolerant techniques. SIU 2016: 2073-2076 - 2015
- [c3]Buse Ustaoglu, Berna Örs Yalçin:
Fault tolerant register file design for MIPS AES-crypto microprocessor. ICECS 2015: 442-445 - [c2]Buse Ustaoglu, Ahmet Cagri Bagbaba, Berna Örs, Inan Erdem:
Creating test environment with UVM for SPI. SIU 2015: 2373-2376 - 2013
- [c1]Ramazan Yeniceri, Buse Ustaoglu, Müstak E. Yalçin:
Throughput enhancement for a new time-delay sampled-data system based True Random Bit Generator. ECCTD 2013: 1-4
Coauthor Index
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