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2020 – today
- 2022
[c14]Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase:
Fault Resilience Techniques for Flash Memory of DNN Accelerators. ITC 2022: 591-600- [c13]Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase:
Fault Resilience Techniques for Flash Memory of DNN Accelerators. ITC-Asia 2022: 1-6
2010 – 2019
- 2015
- [c12]Jin-Hua Hong, Wei-Ling Yi:
Physical design optimizations for a high-resolution third-order sigma-delta modulator. FSKD 2015: 1961-1965 - 2014
- [c11]Jin-Hua Hong, Zong-Yi Chen:
A low-power 10MHz bandwidth continuous-time ΣΔ ADC with Gm-C filter. MWSCAS 2014: 853-856 - [c10]Shyue-Kung Lu, Huai-Min Li, Masaki Hashizume, Jin-Hua Hong, Zheng-Ru Tsai:
Efficient test length reduction techniques for interposer-based 2.5D ICs. VLSI-DAT 2014: 1-4 - 2012
- [c9]Pei-Yung Hsiao, Jin-Hua Hong, Chia-Chen Hsu, Hsiao-Ping Lin, Shih-Shinh Huang:
A Lane Departure Warning System with FPGA modular design. ICVES 2012: 201-204
2000 – 2009
- 2008
- [c8]Jin-Hua Hong, Wen-Jie Li:
A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier. ISVLSI 2008: 483-486 - [c7]Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang:
An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. ISVLSI 2008: 503-506 - 2006
- [c6]Jin-Hua Hong, Bin-Yan Tsai:
A Fast Bit-Interleaving RSA Cryptosystem Based on Radix-4 Cellular-Array Modular Multiplier. APCCAS 2006: 1446-1449 - 2004
- [c5]Jin-Hua Hong, Bin-Yan Tsai, Liang-Te Lu, Shao-Hui Shieh:
A novel radix-4 bit-level modular multiplier for fast RSA cryptosystem. ISCAS (2) 2004: 837-840 - 2003
- [j4]Jin-Hua Hong, Cheng-Wen Wu
:
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 474-484 (2003) - [c4]Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong:
A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers. ISCAS (5) 2003: 365-368 - 2001
- [j3]Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu:
VLSI Design of RSA Cryptosystem Based on the Chinese Remainder Theorem. J. Inf. Sci. Eng. 17(6): 967-980 (2001) - [c3]Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu:
RSA cryptosystem design based on the Chinese remainder theorem. ASP-DAC 2001: 391-395 - 2000
- [j2]Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu:
Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 503-516 (2000) - [c2]Jin-Hua Hong, Cheng-Wen Wu:
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem. ASP-DAC 2000: 565-570
1990 – 1999
- 1998
- [j1]Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu:
Sequential circuit fault simulation using logic emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 724-736 (1998) - 1996
- [c1]Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu:
Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module. Asian Test Symposium 1996: 50-55
Coauthor Index
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