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2010 – 2019
- 2011
[j3]Yu-Cherng Hung, Shao-Hui Shieh, Chiou-Kou Tung:
A Survey of Low-voltage Low-Power Techniques and Challenges for CMOS Digital Circuits. J. Circuits Syst. Comput. 20(1): 89-105 (2011)- [c8]Shao-Hui Shieh, Hsin-Chiang You, Chyi-Yau Shao:
Fabrication of sol-gel-derived zinc oxide thin-film transistor. NEMS 2011: 736-739 - [c7]Hsin-Chiang You, Shiang-Jun Zhang, Shao-Hui Shieh, Chiou-Kou Tung:
Fabricating zinc oxide semiconductor device of flexible substrate by using the spin-coating method. NEMS 2011: 780-783
2000 – 2009
- 2009
- [c6]Ching-Hwa Cheng, Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung:
Design High-Performance and Low-Power Adder Cores with Full-Swing Nodes for Embedded Systems. IIH-MSP 2009: 534-537 - [c5]Yu-Cherng Hung, Min-Ming Kuo, Chiou-Kou Tung, Shao-Hui Shieh:
High-Speed CMOS Chip Design for Manchester and Miller Encoder. IIH-MSP 2009: 538-541 - 2007
- [c4]Chiou-Kou Tung, Yu-Cherng Hung, Shao-Hui Shieh, Guo-Shing Huang:
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System. DDECS 2007: 199-202 - 2006
- [c3]Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai:
High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability. APCCAS 2006: 614-617 - 2004
- [c2]Jin-Hua Hong, Bin-Yan Tsai, Liang-Te Lu, Shao-Hui Shieh:
A novel radix-4 bit-level modular multiplier for fast RSA cryptosystem. ISCAS (2) 2004: 837-840 - 2003
- [j2]Shao-Hui Shieh, Cheng-Wen Wu:
Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition. J. Inf. Sci. Eng. 19(6): 1015-1039 (2003) - 2000
- [j1]Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
:
A fast signature computation algorithm for LFSR and MISR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1031-1040 (2000)
1990 – 1999
- 1996
- [c1]Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu:
A MISR Computation Algorithm for Fast Signature Simulation. Asian Test Symposium 1996: 213-218
Coauthor Index
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