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2010 – 2019
- 2018
[c16]Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
, Mehdi Dehbashi, Ulrike Pfannkuchen:
Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. DDECS 2018: 79-84- 2017
- [c15]Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler:
Machine learning based test pattern analysis for localizing critical power activity areas. DFT 2017: 1-6 - 2016
- [c14]Harshad Dhotre, Mehdi Dehbashi, Ulrike Pfannkuchen, Klaus Hofmann:
Automated Optimization of Scan Chain Structure for Test Compression-Based Designs. ATS 2016: 185-190 - 2015
- [j3]Mehdi Dehbashi, Görschwin Fey:
Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocess. Microsystems 39(3): 157-166 (2015) - 2014
- [c13]Mehdi Dehbashi, Görschwin Fey:
Sat-based speedpath debugging using waveforms. ETS 2014: 1-6 - [c12]Mehdi Dehbashi, Görschwin Fey:
SAT-based speedpath debugging using X traces. IDT 2014: 100-105 - [c11]Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß:
Automated formal verification of X propagation with respect to testability issues. IDT 2014: 106-111 - [c10]Mehdi Dehbashi, Görschwin Fey:
Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs. PDP 2014: 400-404 - [c9]Mehdi Dehbashi, Görschwin Fey:
Debug Automation for Synchronization Bugs at RTL. VLSID 2014: 44-49 - 2013
- [b1]Mehdi Dehbashi:
Debug automation from pre-silicon to post-silicon. University of Bremen, 2013, pp. 1-160 - [j2]Mehdi Dehbashi, Görschwin Fey:
Debug Automation for Logic Circuits Under Timing Variations. IEEE Des. Test 30(6): 60-69 (2013) - [j1]Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated design debugging in a testbench-based verification environment. Microprocess. Microsystems 37(2): 206-217 (2013) - [c8]Mehdi Dehbashi, Görschwin Fey:
Efficient automated speedpath debugging. DDECS 2013: 48-53 - 2012
- [c7]Mehdi Dehbashi, Görschwin Fey:
Automated Post-Silicon Debugging of Failing Speedpaths. Asian Test Symposium 2012: 13-18 - [c6]Mehdi Dehbashi, Görschwin Fey:
Automated debugging from pre-silicon to post-silicon. DDECS 2012: 324-329 - [c5]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD 2012: 431-436 - [c4]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
Functional analysis of circuits under timing variations. ETS 2012: 1 - 2011
- [c3]Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated Design Debugging in a Testbench-Based Verification Environment. DSD 2011: 479-486
2000 – 2009
- 2008
- [c2]Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi:
Fault Effects in FlexRay-Based Networks with Hybrid Topology. ARES 2008: 491-496 - 2007
- [c1]Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand:
Assessment of Message Missing Failures in FlexRay-Based Networks. PRDC 2007: 191-194
Coauthor Index
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