"On Modeling and Evaluation of Logic Circuits under Timing Variations."

Mehdi Dehbashi et al. (2012)

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DOI: 10.1109/DSD.2012.91

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/dsd/DehbashiFRR12
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD 2012: 431-436

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