default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDAndré Sülflow
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2010 – 2019
- 2015
[j5]Nicole Drechsler, André Sülflow, Rolf Drechsler
:
Incorporating user preferences in many-objective optimization using relation ε-preferred. Nat. Comput. 14(3): 469-483 (2015)- [c22]Tino Flenker, André Sülflow, Görschwin Fey:
Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation. ATS 2015: 145-150 - 2014
- [j4]Alexander Finder, André Sülflow, Görschwin Fey:
Latency Analysis for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 643-647 (2014) - 2013
- [j3]Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated design debugging in a testbench-based verification environment. Microprocess. Microsystems 37(2): 206-217 (2013) - [c21]Nicole Drechsler, André Sülflow, Rolf Drechsler:
Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred. IJCCI 2013: 67-74 - 2012
- [c20]Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow:
FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference 2012: 260-265 - 2011
- [j2]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1239-1252 (2011) - [c19]Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated Design Debugging in a Testbench-Based Verification Environment. DSD 2011: 479-486 - [c18]Alexander Finder, André Sülflow, Görschwin Fey:
Latency Analysis for Sequential Circuits. ETS 2011: 129-134 - 2010
- [b1]André Sülflow:
WoLFram - a word level framework for formal verification and its application. University of Bremen, Germany, Shaker 2010, ISBN 978-3-8322-8945-4, pp. 1-190 - [j1]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it Inf. Technol. 52(4): 216-223 (2010) - [c17]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: A Robustness Checker for Digital Circuits. DSD 2010: 226-231 - [c16]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: a robustness checker for digital circuits. DYADEM-FTS@EDCC 2010: 37-38 - [c15]André Sülflow:
Bounded Fault Tolerance Checking. FDL 2010: 71 - [c14]André Sülflow, Rolf Drechsler:
Automatic Fault Localization for Programmable Logic Controllers. FORMS/FORMAT 2010: 247-256 - [c13]André Sülflow, Görschwin Fey, Rolf Drechsler:
Using QBF to increase accuracy of SAT-based debugging. ISCAS 2010: 641-644 - [c12]Görschwin Fey, André Sülflow, Rolf Drechsler:
Towards Unifying Localization and Explanation for Automated Debugging. MTV 2010: 3-8
2000 – 2009
- 2009
- [c11]Görschwin Fey, André Sülflow, Rolf Drechsler:
Computing bounds for fault tolerance using formal techniques. DAC 2009: 190-195 - [c10]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler:
Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331 - [c9]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
Robustness Check for Multiple Faults Using Formal Techniques. DSD 2009: 85-90 - [c8]André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler:
Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL 2009: 298-303 - [c7]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler:
Increasing the Accuracy of SAT-based Debugging. MBMV 2009: 47-56 - [c6]André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler:
WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17 - [i1]Robert Wille, Jean Christoph Jung, André Sülflow, Rolf Drechsler:
SWORD - Module-based SAT Solving. Algorithms and Applications for Next Generation SAT Solvers 2009 - 2008
- [c5]André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler:
Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI 2008: 77-82 - [c4]André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler:
Debugging Design Errors by Using Unsatisfiable Cores. MBMV 2008: 159-168 - 2007
- [c3]André Sülflow, Nicole Drechsler, Rolf Drechsler:
Robust Multi-Objective Optimization in High Dimensional Spaces. EMO 2007: 715-726 - [c2]André Sülflow, Rolf Drechsler:
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. ISMVL 2007: 42 - [c1]André Sülflow, Görschwin Fey, Rolf Drechsler:
Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. MBMV 2007: 101-110
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-24 23:12 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
