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ORCIDChiraag Juvekar
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- affiliation (PhD 2018): Massachusetts Institute of Technology, Cambridge, USA
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2020 – today
- 2023
[c12]Rashmi Agrawal, Leo de Castro, Guowei Yang
, Chiraag Juvekar, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Ajay Joshi:
FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption. HPCA 2023: 882-895- [c11]Rashmi Agrawal, Leo de Castro, Chiraag Juvekar, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Ajay Joshi:
MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption. MICRO 2023: 685-697 - 2022
- [j6]Arslan Riaz, Dylan Nash, Jonathan Ngo, Chiraag Juvekar, Phillip M. Nadeau, Tao Yu, Rabia Tugce Yazicigil:
Security Assessment of Phase-Based Ranging Systems in a Multipath Environment. ACM J. Emerg. Technol. Comput. Syst. 18(4): 66:1-66:19 (2022) - [i9]Rashmi Agrawal, Leo de Castro, Guowei Yang, Chiraag Juvekar, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Ajay Joshi:
FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption. CoRR abs/2207.11872 (2022) - 2021
- [j5]Muhammad Ibrahim Wasiq Khan, Mohamed I. Ibrahim, Chiraag Shashikant Juvekar, Wanyeong Jung, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Ruonan Han:
CMOS THz-ID: A 1.6-mm² Package-Less Identification Tag Using Asymmetric Cryptography and 260-GHz Far-Field Backscatter Communication. IEEE J. Solid State Circuits 56(2): 340-354 (2021) - [c10]Leo de Castro, Chiraag Juvekar, Vinod Vaikuntanathan:
Fast Vector Oblivious Linear Evaluation from Ring Learning with Errors. WAHC@CCS 2021: 29-41 - [i8]Leo de Castro, Rashmi Agrawal, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Chiraag Juvekar, Ajay Joshi:
Does Fully Homomorphic Encryption Need Compute Acceleration? CoRR abs/2112.06396 (2021) - [i7]Leo de Castro, Rashmi Agrawal, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Vinod Vaikuntanathan, Chiraag Juvekar, Ajay Joshi:
Does Fully Homomorphic Encryption Need Compute Acceleration? IACR Cryptol. ePrint Arch. 2021: 1636 (2021) - 2020
- [c9]Mohamed I. Ibrahim, Muhammad Ibrahim Wasiq Khan, Wanyeong Jung, Rabia Tugce Yazicigil, Chiraag Shashikant Juvekar, Anantha P. Chandrakasan, Ruonan Han:
29.8 THzID: A 1.6mm2 Package-Less Cryptographic Identification Tag with Backscattering and Beam-Steering at 260GHz. ISSCC 2020: 454-456 - [i6]Leo de Castro, Chiraag Juvekar, Vinod Vaikuntanathan:
Fast Vector Oblivious Linear Evaluation from Ring Learning with Errors. IACR Cryptol. ePrint Arch. 2020: 685 (2020)
2010 – 2019
- 2019
- [j4]Utsav Banerjee, Andrew Wright, Chiraag Juvekar, Madeleine Waller, Arvind, Anantha P. Chandrakasan:
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications. IEEE J. Solid State Circuits 54(8): 2339-2352 (2019) - [i5]Utsav Banerjee, Chiraag Juvekar, Andrew Wright, Arvind, Anantha P. Chandrakasan:
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications. CoRR abs/1903.04387 (2019) - [i4]Nick Moran, Chiraag Juvekar:
Reconstructing Network Inputs with Additive Perturbation Signatures. CoRR abs/1904.05712 (2019) - [i3]Utsav Banerjee, Andrew Wright, Chiraag Juvekar, Madeleine Waller, Arvind, Anantha P. Chandrakasan:
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications. CoRR abs/1907.04455 (2019) - 2018
- [b1]Chiraag Shashikant Juvekar:
Hardware and protocols for authentication and secure computation. Massachusetts Institute of Technology, Cambridge, USA, 2018 - [j3]Nachiket V. Desai, Chiraag Juvekar, Shubham Chandak, Anantha P. Chandrakasan:
An Actively Detuned Wireless Power Receiver With Public Key Cryptographic Authentication and Dynamic Power Allocation. IEEE J. Solid State Circuits 53(1): 236-246 (2018) - [c8]Chiraag Juvekar, Anantha P. Chandrakasan, Joyce Kwong, Hyung-Min Lee:
A nonvolatile flip-flop-enabled cryptographic wireless authentication tag with per-query key update and power-glitch attack countermeasures. ASP-DAC 2018: 279-280 - [c7]Utsav Banerjee, Chiraag Juvekar, Andrew Wright, Arvind, Anantha P. Chandrakasan:
An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications. ISSCC 2018: 42-44 - [c6]Chiraag Juvekar, Vinod Vaikuntanathan, Anantha P. Chandrakasan:
GAZELLE: A Low Latency Framework for Secure Neural Network Inference. USENIX Security Symposium 2018: 1651-1669 - [i2]Chiraag Juvekar, Vinod Vaikuntanathan, Anantha P. Chandrakasan:
Gazelle: A Low Latency Framework for Secure Neural Network Inference. CoRR abs/1801.05507 (2018) - [i1]Chiraag Juvekar, Vinod Vaikuntanathan, Anantha P. Chandrakasan:
GAZELLE: A Low Latency Framework for Secure Neural Network Inference. IACR Cryptol. ePrint Arch. 2018: 73 (2018) - 2017
- [j2]Hyung-Min Lee, Chiraag Juvekar, Joyce Kwong, Anantha P. Chandrakasan:
A Nonvolatile Flip-Flop-Enabled Cryptographic Wireless Authentication Tag With Per-Query Key Update and Power-Glitch Attack Countermeasures. IEEE J. Solid State Circuits 52(1): 272-283 (2017) - [c5]Utsav Banerjee, Chiraag Juvekar, Samuel H. Fuller, Anantha P. Chandrakasan:
eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things. GLOBECOM 2017: 1-6 - [c4]Nachiket V. Desai, Chiraag Juvekar, Shubham Chandak, Anantha P. Chandrakasan:
21.8 An actively detuned wireless power receiver with public key cryptographic authentication and dynamic power allocation. ISSCC 2017: 366-367 - 2016
- [c3]Chiraag Juvekar, Hyung-Min Lee, Joyce Kwong, Anantha P. Chandrakasan:
16.2 A Keccak-based wireless authentication tag with per-query key update and power-glitch attack countermeasures. ISSCC 2016: 290-291 - 2014
- [j1]Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications. IEEE J. Solid State Circuits 49(1): 61-72 (2014) - [p1]Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
Decoder Hardware Architecture for HEVC. High Efficiency Video Coding 2014: 303-341 - 2013
- [c2]Chao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications. ISSCC 2013: 162-163 - [c1]Chao-Tsung Huang, Chiraag Juvekar, Mehul Tikekar, Anantha P. Chandrakasan:
HEVC interpolation filter architecture for quad full HD decoding. VCIP 2013: 1-5
Coauthor Index
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