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2020 – today
- 2023
[j4]Lu Zhang
, Dejun Mu, Yuxuan Huang, Jingyu Wang, Yifan He, Yaolei Li, Lizhou Liu, Kaiwei Zou, Huazhong Yang, Yongpan Liu:
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1124-1128 (2023)- [j3]Yaolei Li, Jinshan Yue, Jingyu Wang, Chen Tang, Yifan He, Wenbin Jia, Kaiwei Zou, Lu Zhang, Huazhong Yang, Yongpan Liu:
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1179-1183 (2023) - [c5]Wen Li, Ying Wang, Kaiwei Zou, Huawei Li, Xiaowei Li:
Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors. ATS 2023: 1-6 - [c4]Kaiwei Zou, Songyun Qu, Wen Li, Ying Wang, Huawei Li, Yongpan Liu:
Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators. ICPADS 2023: 1123-1130 - 2022
- [j2]Kaiwei Zou, Ying Wang, Long Cheng, Songyun Qu, Huawei Li, Xiaowei Li:
CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures. IEEE Trans. Computers 71(7): 1626-1639 (2022) - [j1]Yuxuan Huang, Yifan He, Jingyu Wang, Jinshan Yue, Lu Zhang, Kaiwei Zou, Huazhong Yang, Yongpan Liu:
Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3144-3148 (2022)
2010 – 2019
- 2019
- [c3]Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li:
Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. DATE 2019: 1172-1177 - 2018
- [c2]Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li:
XORiM: A case of in-memory bit-comparator implementation and its performance implications. ASP-DAC 2018: 349-354 - 2014
- [c1]Honghai Feng, Yanyan Chen, Kaiwei Zou, Lijuan Liu, Qiannan Zhu, Zhuo Ran, Li Yao, Lijin Ji, Sai Liu:
A New Rough Set Based Classification Rule Generation Algorithm(RGA). IEA/AIE (1) 2014: 369-378
Coauthor Index
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