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2020 – today
- 2024
[j4]Ke Yu
, Sunmean Kim, Jun Rim Choi:
Trends and Challenges in Computing-in-Memory for Neural Network Model: A Review From Device Design to Application-Side Optimization. IEEE Access 12: 186679-186702 (2024)- 2023
- [j3]Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang:
Optimizing Ternary Multiplier Design With Fast Ternary Adder. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 766-770 (2023) - 2022
- [c11]Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee:
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. DATE 2022: 1077-1082 - 2021
- [j2]Sunmean Kim, Yesung Kang, Seunghan Baek, Youngchang Choi, Seokhyeong Kang:
Low-Power Ternary Multiplication Using Approximate Computing. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2947-2951 (2021) - [c10]Youngchang Choi, Sunmean Kim, Kyongsu Lee, Seokhyeong Kang:
Design and Analysis of a Low-Power Ternary SRAM. ISCAS 2021: 1-4 - [c9]Jiyoung Min, Sunmean Kim, Seokhyeong Kang:
Memcapacitor based Minimum and Maximum Gate Design. ISOCC 2021: 75-76 - [c8]Minjeong Choi, Youngchang Choi, Sunmean Kim, Seokhyeong Kang:
Ternary Sense Amplifier Design for Ternary SRAM. ISOCC 2021: 151-152 - [i1]Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee:
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. CoRR abs/2111.07584 (2021) - 2020
- [j1]Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang:
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3138-3151 (2020) - [c7]Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, Byoung Hun Lee:
Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. ISMVL 2020: 155-158 - [c6]Seunghan Baek, Sunmean Kim, Youngchang Choi, Seokhyeong Kang:
MTCMOS-based Ternary to Binary Converter. ISOCC 2020: 5-6 - [c5]Youngchang Choi, Sunmean Kim, Seunghan Baek, Seokhyeong Kang:
Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion. ISOCC 2020: 254-255
2010 – 2019
- 2019
- [c4]Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang:
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. ISMVL 2019: 37-42 - [c3]Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang:
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm. ISMVL 2019: 158-163 - [c2]Sunghye Park, Sunmean Kim, Seokhyeong Kang:
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU. ISOCC 2019: 25-26 - 2018
- [c1]Sunmean Kim, Taeho Lim, Seokhyeong Kang:
An optimal gate design for the synthesis of ternary logic circuits. ASP-DAC 2018: 476-481
Coauthor Index
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