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ORCIDGitanjali Swamy
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1990 – 1999
- 1998
[c7]Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton:
Efficient Verification and Synthesis using Design Commonalities. VLSI Design 1998: 542-551- 1997
- [c6]Gitanjali Swamy:
Formal Verification of Digital Systems. VLSI Design 1997: 213-217 - 1996
- [c5]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards
, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS: A System for Verification and Synthesis. CAV 1996: 428-432 - [c4]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS. FMCAD 1996: 248-256 - 1995
- [c3]Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal:
Incremental methods for FSM traversal. ICCD 1995: 590-595 - 1994
- [c2]Gitanjali Swamy, Robert K. Brayton:
Incremental formal design verification. ICCAD 1994: 458-465 - [c1]Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton:
Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. ICCD 1994: 255-261
Coauthor Index
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