default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDAllen C.-H. Wu
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2021
[j22]Chin-Yu Sun
, Allen C.-H. Wu, TingTing Hwang:
A novel privacy-preserving deep learning scheme without a cryptography component. Comput. Electr. Eng. 94: 107325 (2021)- [c43]Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang:
A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). ASP-DAC 2021: 210-215
2010 – 2019
- 2019
- [c42]Pei-An Ho, Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang:
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs. SoCC 2019: 236-241 - [c41]Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang:
Crosstalk-aware TSV-buffer Insertion in 3D IC. SoCC 2019: 400-405 - [i1]Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang:
A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component. CoRR abs/1908.07701 (2019) - 2017
- [j21]Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang:
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 820-832 (2017) - 2016
- [c40]Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang:
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. DATE 2016: 79-84 - 2015
- [c39]Ruimin Lyu, Haojie Hao, Wei Chen, Yuan Liu, Feng Wang, Allen C.-H. Wu:
Elastylus: flexible haptic painting stylus. SIGGRAPH Asia Emerging Technologies 2015: 10:1-10:3
2000 – 2009
- 2007
- [j20]Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu:
Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 564-573 (2007) - 2006
- [j19]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11(4): 880-889 (2006) - [j18]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 81-85 (2006) - [c38]Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu:
Performance-driven crosstalk elimination at post-compiler level. ISCAS 2006 - 2005
- [c37]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) 2005: 3311-3314 - [c36]Bing-Fei Wu, Chuan-Tsai Lin, Chao-Jung Chen, Tze-Chiuan Lai, Hsueh-Lung Liao, Allen C.-H. Wu:
A fast lane and vehicle detection approach for autonomous vehicles. SIP 2005: 305-310 - 2004
- [c35]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
Decomposition of Instruction Decoder for Low Power Design. DATE 2004: 664-665 - 2003
- [c34]Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang:
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE 2003: 11102-11103 - [c33]Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang:
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE 2003: 11134-11135 - 2002
- [c32]M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu:
A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers. ISCAS (1) 2002: 81-84 - [c31]Jerry C.-Y. Kao, C.-F. Su, Allen C.-H. Wu:
High-performance FIR generation based on a timing-driven architecture and component selection method. ISCAS (4) 2002: 759-762 - 2001
- [c30]Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu:
An RTL design-space exploration method for high-level applications. ASP-DAC 2001: 162-168 - 2000
- [j17]Wen-Jong Fang, Allen C.-H. Wu:
Multiway FPGA partitioning by fully exploiting design hierarchy. ACM Trans. Design Autom. Electr. Syst. 5(1): 34-50 (2000) - [j16]Chi-Hong Hwang, Allen C.-H. Wu:
A predictive system shutdown method for energy saving of event-driven computation. ACM Trans. Design Autom. Electr. Syst. 5(2): 226-241 (2000) - [j15]Allen C.-H. Wu, Nikil D. Dutt:
Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). IEEE Trans. Very Large Scale Integr. Syst. 8(5): 469-471 (2000) - [c29]Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud:
Embedded tutorial: essential issues for IP reuse. ASP-DAC 2000: 37-42 - [c28]Chien-Chu Kuo, Allen C.-H. Wu:
Delay Budgeting for a Timing-Closure-Driven Design Method. ICCAD 2000: 202-207
1990 – 1999
- 1999
- [j14]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin:
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 475-483 (1999) - [j13]Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen:
EmGen-a module generator for logic emulation applications. IEEE Trans. Very Large Scale Integr. Syst. 7(4): 488-492 (1999) - [c27]Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu:
A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. ASP-DAC 1999: 351-354 - [c26]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin:
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC 1999: 262-267 - [c25]Kun-Ming Ho, Allen C.-H. Wu:
Module Generation of High Performance FPGA-Based Multipliers. FPGA 1999: 251 - 1998
- [j12]Wen-Jong Fang, Allen C.-H. Wu:
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs. IEEE Des. Test Comput. 15(2): 65-72 (1998) - [c24]Wen-Jong Fang, Allen C.-H. Wu:
Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. DAC 1998: 283-286 - [c23]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin:
Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD 1998: 12-17 - 1997
- [j11]Yuh-Sheng Lee, Allen C.-H. Wu:
A performance and routability-driven router for FPGAs considering path delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(2): 179-185 (1997) - [j10]Wen-Jong Fang, Allen C.-H. Wu:
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1188-1195 (1997) - [j9]Yann-Rue Lin, Cheng-Tsung Hwang, Allen C.-H. Wu:
Scheduling techniques for variable voltage low power designs. ACM Trans. Design Autom. Electr. Syst. 2(2): 81-97 (1997) - [j8]Allen C.-H. Wu:
Datapath Optimization Using Layout Information: An Empirical Study. VLSI Design 5(2): 195-209 (1997) - [c22]Chi-Hong Hwang, Allen C.-H. Wu:
An entropy measure for power estimation of Boolean functions. ASP-DAC 1997: 101-106 - [c21]Wei-Liang Ing, Cheng-Tsung Hwang, Allen C.-H. Wu:
Evaluating cost-performance tradeoffs for system level applications. ASP-DAC 1997: 233-238 - [c20]Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin:
DP-Gen: a datapath generator for multiple-FPGA applications. ASP-DAC 1997: 563-568 - [c19]Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen:
A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. DAC 1997: 101-106 - [c18]Wen-Jong Fang, Allen C.-H. Wu:
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. DAC 1997: 518-521 - [c17]Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen:
Module Generation of Complex Macros for Logic-Emulation Applications. FPGA 1997: 69-75 - [c16]Chi-Hong Hwang, Allen C.-H. Wu:
A predictive system shutdown method for energy saving of event-driven computation. ICCAD 1997: 28-32 - [c15]Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin:
Preserving HDL synthesis hierarchy for cell placement. ISPD 1997: 169-174 - 1996
- [j7]Tsing-Gen Lee, Wen-Jong Fang, Allen C.-H. Wu:
The Design and Inplementation of a Cooperative Design-view Environment for Interactive Partitioning Applications. Softw. Pract. Exp. 26(10): 1141-1160 (1996) - [c14]Wen-Jong Fang, Allen C.-H. Wu:
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. ICCAD 1996: 638-643 - 1995
- [j6]Allen C.-H. Wu, Youn-Long Lin:
High-Level Synthesis -A Tutorial. IEICE Trans. Inf. Syst. 78-D(3): 209-218 (1995) - [j5]Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin:
TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 371-374 (1995) - [j4]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1076-1084 (1995) - [c13]Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee:
EMPAR: an interactive synthesis environment for hardware emulations. ASP-DAC 1995 - [c12]Yuh-Sheng Lee, Allen C.-H. Wu:
A Performance and Routability Driven Router for FPGAs Considering Path Delays. DAC 1995: 557-561 - 1994
- [j3]Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski:
A transformation-based method for loop folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 439-450 (1994) - [c11]Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin:
A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC 1994: 277-281 - [c10]Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
State Assignment for Power and Area Minimization. ICCD 1994: 250-254 - 1993
- [c9]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127 - 1992
- [b1]Daniel D. Gajski, Nikil D. Dutt, Allen C.-H. Wu:
Youn-Long Steve Lin. Springer 1992, ISBN 978-1-4613-6617-1, pp. 1-359 - [j2]Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu:
Layout placement for sliced architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1): 102-114 (1992) - [j1]Allen C.-H. Wu, Daniel D. Gajski:
Partitioning algorithms for layout synthesis from register-transfer netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4): 453-463 (1992) - [c8]Viraphol Chaiyakul, Allen C.-H. Wu, Daniel D. Gajski:
Timing models for high-level synthesis. EURO-DAC 1992: 60-65 - [c7]Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin:
An effective methodology for functional pipelining. ICCAD 1992: 230-233 - [c6]Allen C.-H. Wu, Tedd Hadley, Daniel Gajski:
An efficient multi-view design model for real-time interactive synthesis. ICCAD 1992: 328-331 - [c5]Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul:
Accurate layout area and delay modeling for system level design. ICCAD 1992: 355-361 - 1991
- [c4]Allen C.-H. Wu, Daniel D. Gajski:
Glue-logic partitioning for floorplans with a rectilinear datapath. EURO-DAC 1991: 162-166 - [c3]Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski:
Layout-Area Models for High-Level Synthesis. ICCAD 1991: 34-37 - 1990
- [c2]Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski:
A new algorithm for transistor sizing in CMOS circuits. EURO-DAC 1990: 589-593 - [c1]Allen C.-H. Wu, Daniel Gajski:
Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. ICCAD 1990: 144-147
Coauthor Index
aka: Daniel D. Gajski
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-16 00:37 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
