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2020 – today
- 2023
[c10]Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng:
Live Demonstration: A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. ISCAS 2023: 1- [c9]Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng:
A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. ISCAS 2023: 1-5
2010 – 2019
- 2013
- [j6]Shin-Kai Chen, Chih-Wei Liu, Tsung-Yi Wu, An-Chi Tsai:
Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM). IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(10): 2631-2643 (2013) - 2012
- [c8]Tsung-Yi Wu, Yi-Chieh Chang, Shang-Ti Chen, I-Tsun Chiang:
A Preliminary Study on Using Augmented Virtuality to Improve Training for Intercollegiate Archers. DIGITEL 2012: 212-216 - 2010
- [j5]Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin:
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2581-2589 (2010) - [c7]Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin:
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. ASP-DAC 2010: 444-449
2000 – 2009
- 2009
- [j4]How-Rern Lin, Wei-Hao Chiu, Tsung-Yi Wu:
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates. IEICE Trans. Electron. 92-C(4): 386-390 (2009) - [j3]Tsung-Yi Wu, Liang-Ying Lu:
Low-Leakage and Low-Power Implementation of High-Speed Logic Gates. IEICE Trans. Electron. 92-C(4): 401-408 (2009) - 2008
- [c6]Jiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen:
IR Drop Reduction via a Flip-Flop Resynthesis Technique. ISQED 2008: 78-83 - 2007
- [j2]Tsung-Yi Wu, Jr-Luen Tzeng:
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2718-2726 (2007) - [c5]Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen:
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. ASP-DAC 2007: 672-677 - 2001
- [c4]Nai-Yin Sung, Tsung-Yi Wu:
A Method of Embedded Memory Access Time Measurement. ISQED 2001: 462-465
1990 – 1999
- 1996
- [j1]Tsung-Yi Wu, Youn-Long Lin:
Register minimization beyond sharing among variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1583-1587 (1996) - [c3]Youn-Long Lin, Tsung-Yi Wu:
Storage optimization by replacing some flip-flops with latches. EURO-DAC 1996: 296-301 - 1995
- [c2]Tsung-Yi Wu, Youn-Long Lin:
Register Minimization beyond Sharing among Variables. DAC 1995: 164-169 - 1994
- [c1]Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin:
A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC 1994: 277-281
Coauthor Index
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