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2010 – 2019
- 2010
[j4]Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin:
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2581-2589 (2010)- [c4]Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin:
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. ASP-DAC 2010: 444-449
2000 – 2009
- 2009
- [j3]How-Rern Lin, Wei-Hao Chiu, Tsung-Yi Wu:
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates. IEICE Trans. Electron. 92-C(4): 386-390 (2009)
1990 – 1999
- 1999
- [j2]How-Rern Lin, TingTing Hwang:
On determining sensitization criterion in an iterative gate sizing process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 231-238 (1999) - 1996
- [j1]How-Rern Lin, Yu-Chin Hsu, TingTing Hwang:
Cell height driven transistor sizing in a cell based static CMOS module design. IEEE J. Solid State Circuits 31(5): 668-676 (1996) - 1995
- [c3]How-Rern Lin, TingTing Hwang:
Power recduction by gate sizing with path-oriented slack calculation. ASP-DAC 1995 - 1994
- [c2]How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang:
Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429 - [c1]How-Rern Lin, TingTing Hwang:
Dynamical identification of critical paths for iterative gate sizing. ICCAD 1994: 481-484
Coauthor Index
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