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ORCIDJitendra Khare
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2000 – 2009
- 2006
[c20]Jitendra Khare, Amit B. Shah, Ashok Raman, Girish Rayas:
Embedded Memory Field Returns - Trials and Tribulations. ITC 2006: 1-6- 2004
- [c19]Hans T. Heineken, Jitendra Khare:
Test Strategies For a 40Gbps Framer SoC. ITC 2004: 758-763 - [c18]Jitendra Khare:
Memory Yield Improvement - SoC Design Perspective. ITC 2004: 1445 - 2003
- [c17]Jitendra Khare:
DFM - A Fabless Perspective. ITC 2003: 1317 - 2001
- [c16]John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC 2001: 258-267 - [c15]John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare:
Enabling Embedded Memory Diagnosis via Test Response Compression. VTS 2001: 292-298 - 2000
- [c14]Jitendra Khare, Hans T. Heineken, Manuel d'Abreu:
Cost Trade-Offs in System On Chip Designs. VLSI Design 2000: 178-184 - [c13]Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken:
Manufacturability and Testability Oriented Synthesis. VLSI Design 2000: 185-191 - [c12]Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, Manuel d'Abreu:
Maximizing Wafer Productivity Through Layout Optimization. VLSI Design 2000: 192-197 - [c11]A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su:
Test and Debug of Networking SoCs: A Case Study. VTS 2000: 121-126
1990 – 1999
- 1998
- [c10]Hans T. Heineken, Jitendra Khare, Manuel d'Abreu:
Manufacturability analysis of standard cell libraries. CICC 1998: 321-324 - [c9]Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare:
Design-Manufacturing Interface: Part I - Vision. DATE 1998: 550-556 - [c8]Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon:
Design-Manufacturing Interface: Part II - Applications. DATE 1998: 557-562 - 1997
- [c7]Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface. DAC 1997: 321-326 - 1996
- [c6]Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag:
Design for manufacturability in submicron domain. ICCAD 1996: 690-697 - [c5]Jitendra Khare, Wojciech Maly, Nathan Tiday:
Fault characterization of standard cell libraries using inductive contamination. VTS 1996: 405-413 - 1995
- [c4]Jitendra Khare, Wojciech Maly:
Inductive Contamination Analysis (ICA) with SRAM Application. ITC 1995: 552-560 - [c3]Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar:
Testability-oriented channel routing. VLSI Design 1995: 208-213 - 1993
- [c2]Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly:
Estimation of reject ratio in testing of combinatorial circuits. VTS 1993: 319-325 - 1992
- [c1]Derek Feltham, Jitendra Khare, Wojciech Maly:
Design for testability view on placement and routing. EURO-DAC 1992: 382-387
Coauthor Index
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