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ORCIDSaghir A. Shaikh
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2010 – 2019
- 2016
[c15]Salem Abdennadher, Saghir A. Shaikh:
Practices in High-Speed IO testing. ETS 2016: 1-8- 2014
- [c14]Stephen Sunter, Saghir A. Shaikh, Qing Lin:
Fast BIST of I/O Pin AC specifications and inter-chip delays. ITC 2014: 1-8 - 2013
- [c13]Saghir A. Shaikh:
Innovative practices session 3C: Harnessing the challenges of testability and debug of high speed I/Os. VTS 2013: 1
2000 – 2009
- 2007
- [j2]Salem Abdennadher, Saghir A. Shaikh:
Practices in Mixed-Signal and RF IC Testing. IEEE Des. Test Comput. 24(4): 332-339 (2007) - 2005
- [c12]Salem Abdennadher, Saghir A. Shaikh:
Practices in Testing of Mixed-Signal and RF SoCs. Asian Test Symposium 2005: 467 - [c11]Salem Abdennadher, Saghir A. Shaikh:
Challenges in High Speed Interface Testing. Asian Test Symposium 2005: 468 - 2004
- [c10]Saghir A. Shaikh:
IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver. ITC 2004: 543-550 - 2001
- [c9]John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC 2001: 258-267 - 2000
- [c8]Charles Ouyang, Kyungsuk Ryu, Hans T. Heineken, Jitu Khare, Saghir A. Shaikh, Manuel d'Abreu:
Wire planning for performance and yield enhancement. CICC 2000: 113-116 - [c7]Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken:
Manufacturability and Testability Oriented Synthesis. VLSI Design 2000: 185-191 - [c6]Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, Manuel d'Abreu:
Maximizing Wafer Productivity Through Layout Optimization. VLSI Design 2000: 192-197 - [c5]A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su:
Test and Debug of Networking SoCs: A Case Study. VTS 2000: 121-126
1990 – 1999
- 1998
- [j1]Arun Swaminathan, Saghir A. Shaikh, K. Suzanne Barber:
Design of an experience-based assembly sequence planner for mechanical assemblies. Robotica 16(3): 265-283 (1998) - 1997
- [c4]Saghir A. Shaikh, Stephen A. Szygenda:
Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. Annual Simulation Symposium 1997: 64-74 - [c3]Youngmin Hur, Saghir A. Shaikh, Silvian Goldenberg, Dominik Kacprzak, Stephen A. Szygenda:
Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. Annual Simulation Symposium 1997: 168-176 - 1996
- [c2]Saghir A. Shaikh, Silvian Goldenberg, Stephen A. Szygenda:
CON2FERS: A Concurrent Concurrent Fault and Design Error Simulator. PDPTA 1996: 109-112 - 1995
- [c1]Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda:
Statistics on concurrent fault and design error simulation. ICCD 1995: 622-627
Coauthor Index
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