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ORCIDAnmol Mathur
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2020 – today
- 2022
[c16]Satya Kumar Vankayala, Swaraj Kumar, Thirumulanathan D, Anmol Mathur, Seungil Yoon, Issaac Kommineni:
Deep-Learning Based Beam Selection Technique for 6G Millimeter Wave Communication. PIMRC 2022: 1380-1385
2010 – 2019
- 2012
- [j6]Susan Carver, Anmol Mathur, Lalit Sharma, Prasad Subbarao, Steve Urish, Qi Wang:
Low-Power Design Using the Si2 Common Power Format. IEEE Des. Test Comput. 29(2): 62-70 (2012)
2000 – 2009
- 2009
- [j5]Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal Urard:
Functional Equivalence Verification Tools in High-Level Synthesis Flows. IEEE Des. Test Comput. 26(4): 88-95 (2009) - [c15]Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma:
Non-cycle-accurate sequential equivalence checking. DAC 2009: 460-465 - [c14]Anmol Mathur, Qi Wang:
Power Reduction Techniques and Flows at RTL and System Level. VLSI Design 2009: 28-29 - 2007
- [c13]Anmol Mathur, Venkat Krishnaswamy:
Design for Verification in System-level Models and RTL. DAC 2007: 193-198 - 2006
- [c12]Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra:
Sequential Equivalence Checking. VLSI Design 2006: 18-19 - 2005
- [c11]Alfred Kölbl, Yuan Lu, Anmol Mathur:
Embedded tutorial: formal equivalence checking between system-level models and RTL. ICCAD 2005: 965-971 - 2003
- [c10]G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja:
Graph Transformations for Improved Tree Height Reduction. VLSI Design 2003: 474-479 - 2001
- [c9]Anmol Mathur, Sanjeev Saluja:
Improved Merging of Datapath Operators using Information Content and Required Precision Analysis. DAC 2001: 462-467
1990 – 1999
- 1998
- [j4]Anmol Mathur, Ali Dasdan, Rajesh K. Gupta:
Rate analysis for embedded systems. ACM Trans. Design Autom. Electr. Syst. 3(3): 408-436 (1998) - [j3]Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. ACM Trans. Design Autom. Electr. Syst. 3(4): 600-625 (1998) - [c8]Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
An Implicit Algorithm for Finding Steady States and its Application to FSM Verification. DAC 1998: 611-614 - [c7]Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
Efficient equivalence checking of multi-phase designs using retiming. ICCAD 1998: 557-562 - 1997
- [j2]Anmol Mathur, C. L. Liu:
Timing-driven placement for regular architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6): 597-608 (1997) - [c6]Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
An Efficient Assertion Checker for Combinational Properties. DAC 1997: 734-739 - [c5]Ali Dasdan, Anmol Mathur, Rajesh K. Gupta:
RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. ED&TC 1997: 2-6 - 1996
- [j1]Anmol Mathur, Edward M. Reingold:
Generalized Kraft's Inequality and Discrete k-Modal Search. SIAM J. Comput. 25(2): 420-447 (1996) - [c4]Anmol Mathur
, C. L. Liu:
Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. ED&TC 1996: 165-169 - 1995
- [c3]Anmol Mathur, Kuang-Chien Chen, C. L. Liu:
Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. FPGA 1995: 118-124 - [c2]Anmol Mathur, Kuang-Chien Chen, C. L. Liu:
Re-engineering of timing constrained placements for regular architectures. ICCAD 1995: 485-490 - 1994
- [c1]Anmol Mathur, C. L. Liu:
Compression-relaxation: a new approach to performance driven placement for regular architectures. ICCAD 1994: 130-136
Coauthor Index
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