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ORCIDDavid Andrews 0001
David L. Andrews 0001
Person information
- affiliation: University of Arkansas, Computer Science and Computer Engineering Department, Fayetteville, AR, USA
- affiliation (2000 - 2008): University of Kansas, Lawrence, KS, USA
- affiliation (1992 - 2000): University of Arkansas, Fayetteville, AR, USA
- affiliation (PhD 1992): Syracuse University, NY, USA
Other persons with the same name
- David Andrews — disambiguation page
- David L. Andrews — disambiguation page
- David L. Andrews 0002
![[0000-0002-5903-0787]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-5903-0787")
— University of East Anglia, School of Chemistry, Norwich, UK
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2020 – today
- 2024
[c58]M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators. FCCM 2024: 223- [c57]Tendayi Kamucheka, David Andrews:
Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design of Deep-Learning Accelerators. FCCM 2024: 237-238 - [c56]M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
IMAGine: An In-Memory Accelerated GEMV Engine Overlay. FPL 2024: 220-226 - [i9]Ehsan Kabir, Jason D. Bakos, David Andrews, Miaoqing Huang:
ProTEA: Programmable Transformer Encoder Acceleration on FPGA. CoRR abs/2409.13975 (2024) - [i8]Ehsan Kabir, M. D. Arafat Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang:
FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs. CoRR abs/2409.14023 (2024) - [i7]M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
IMAGine: An In-Memory Accelerated GEMV Engine Overlay. CoRR abs/2410.04367 (2024) - [i6]M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators. CoRR abs/2410.07546 (2024) - 2023
- [c55]M. D. Arafat Kabir, Joshua Hollis, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews:
Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays. FCCM 2023: 224 - [c54]M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews:
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? FPL 2023: 109-115 - [c53]Ehsan Kabir, Daniel Coble, Joud N. Satme, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang:
Accelerating LSTM-Based High-Rate Dynamic System Models. FPL 2023: 327-332 - [i5]M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews:
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? CoRR abs/2308.03914 (2023) - [i4]Ehsan Kabir, Daniel Coble, Joud N. Satme, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang:
Accelerating LSTM-based High-Rate Dynamic System Models. CoRR abs/2309.00801 (2023) - 2022
- [c52]Ehsan Kabir, Arpan Poudel, Zeyad Aklah, Miaoqing Huang, David Andrews:
A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA. ARC 2022: 32-46 - [c51]Atiyehsadat Panahi, Ehsan Kabir, Austin R. J. Downey, David Andrews, Miaoqing Huang, Jason D. Bakos:
High-Rate Machine Learning for Forecasting Time-Series Signals. FCCM 2022: 1-9 - [c50]Tendayi Kamucheka, Alexander Nelson, David Andrews, Miaoqing Huang:
A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm. FPT 2022: 1 - [i3]Tendayi Kamucheka, Alexander Nelson, David Andrews, Miaoqing Huang:
A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm. IACR Cryptol. ePrint Arch. 2022: 1547 (2022) - 2021
- [c49]Atiyehsadat Panahi, Suhail Basalama, Ange-Thierry Ishimwe, Joel Mandebi Mbongue, David Andrews:
A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications. FPL 2021: 24-27 - [i2]Tendayi Kamucheka, Michael Fahr, Tristen Teague, Alexander Nelson, David Andrews, Miaoqing Huang:
Power-based Side Channel Attack Analysis on PQC Algorithms. IACR Cryptol. ePrint Arch. 2021: 1021 (2021) - 2020
- [c48]Haoyan Liu, Atiyehsadat Panahi, David Andrews, Alexander Nelson:
FPGA-Based Gesture Recognition with Capacitive Sensor Array using Recurrent Neural Networks. FCCM 2020: 225 - [c47]Suhail Basalama, Atiyehsadat Panahi, Ange-Thierry Ishimwe, David Andrews:
SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices. ICDIS 2020: 141-147 - [c46]Haoyan Liu, Atiyehsadat Panahi, David Andrews, Alexander Nelson:
An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks. FPT 2020: 296-297
2010 – 2019
- 2019
- [j11]Tim Hansmeier, Marco Platzner, Md Jubaer Hossain Pantho, David Andrews:
An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. J. Signal Process. Syst. 91(11-12): 1259-1272 (2019) - [c45]Atiyehsadat Panahi, Keaten Stokke, David Andrews:
A Library of FSM-based Floating-Point Arithmetic Functions on FPGAs. ReConFig 2019: 1-8 - [e3]David Andrews, René Cumplido, Claudia Feregrino, Marco Platzner:
2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019. IEEE 2019, ISBN 978-1-7281-1957-1 [contents] - 2018
- [c44]Joel Mandebi Mbongue, Festus Hategekimana, Danielle Tchuinkou Kwadjo, David Andrews, Christophe Bobda:
FPGAVirt: A Novel Virtualization Framework for FPGAs in the Cloud. IEEE CLOUD 2018: 862-865 - [c43]Tim Hansmeier, Marco Platzner, David Andrews:
An FPGA/HMC-Based Accelerator for Resolution Proof Checking. ARC 2018: 153-165 - [c42]Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews, Marjan Asadinia:
Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer. FCCM 2018: 217 - [c41]Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews:
Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers. FPT 2018: 342-345 - [e2]David Andrews, René Cumplido, Claudia Feregrino, Dirk Stroobandt:
2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018. IEEE 2018, ISBN 978-1-7281-1968-7 [contents] - 2016
- [c40]Sen Ma, Zeyad Aklah, David Andrews:
Run time interpretation for creating custom accelerators. DATE 2016: 900-905 - [c39]Sen Ma, Zeyad Aklah, David Andrews:
Just In Time Assembly of Accelerators. FPGA 2016: 173-178 - [c38]Hongyuan Ding, Sen Ma, Miaoqing Huang, David Andrews:
OOGen: An Automated Generation Tool for Custom MPSoC Architectures Based on Object-Oriented Programming Methods. IPDPS Workshops 2016: 233-240 - [c37]Sen Ma, David Andrews, Shanyuan Gao, Jaime Cummins:
Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloud. ReConFig 2016: 1-6 - [c36]David Andrews, Marco Platzner:
Programming models for reconfigurable manycore systems. ReCoSoC 2016: 1-8 - [i1]Zeyad Aklah, Sen Ma, David Andrews:
A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators. CoRR abs/1603.01187 (2016) - 2015
- [c35]Zeyad Aklah, David Andrews:
A Flexible Multilayer Perceptron Co-processor for FPGAs. ARC 2015: 427-434 - [c34]Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne:
Automatic support for multi-module parallelism from computational patterns. FPL 2015: 1-8 - [c33]Sen Ma, Zeyad Aklah, David Andrews:
A run time interpretation approach for creating custom accelerators. FPL 2015: 1-4 - [c32]Sen Ma, Hongyuan Ding, Miaoqing Huang, David Andrews:
Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architectures. ReConFig 2015: 1-6 - 2014
- [j10]David Andrews:
Operating Systems Research for Reconfigurable Computing. IEEE Micro 34(1): 54-58 (2014) - [c31]Sen Ma, David Andrews:
On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only). FPGA 2014: 253 - [c30]Eugene Cartwright, Alborz Sadeghian, Sen Ma, David Andrews:
Achieving portability and efficiency over chip heterogeneous multiprocessor systems. FPL 2014: 1-4 - 2013
- [j9]Miaoqing Huang, David Andrews:
Modular Design of Fully Pipelined Reduction Circuits on FPGAs. IEEE Trans. Parallel Distributed Syst. 24(9): 1818-1826 (2013) - 2012
- [c29]Sen Ma, Miaoqing Huang, Eugene Cartwright, David Andrews:
Scalable Memory Hierarchies for Embedded Manycore Systems. ARC 2012: 151-162 - [c28]Eugene Cartwright, Azad Fahkari, Sen Ma, Christina Smith, Miaoqing Huang, David Andrews, Jason Agron:
Automating the design of mLUT MPSoPC FPGAs in the cloud. FPL 2012: 231-236 - [c27]Sen Ma, Miaoqing Huang, David Andrews:
Developing application-specific multiprocessor platforms on FPGAs. ReConFig 2012: 1-6 - 2011
- [j8]Jorge L. Ortiz, David Andrews:
A Streaming High-Throughput Linear Sorter System with Contention Buffering. Int. J. Reconfigurable Comput. 2011: 963539:1-963539:12 (2011) - [c26]Eugene Cartwright, Sen Ma, David Andrews, Miaoqing Huang:
Creating HW/SW co-designed MPSoPC's from high level programming models. HPCS 2011: 554-560 - 2010
- [c25]David Andrews, Christian Plessl:
Configurable Processor Architectures: History and Trends. ERSA 2010: 165 - [c24]Jason Agron, David Andrews:
Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive. FCCM 2010: 39-46 - [c23]Miaoqing Huang, David Andrews:
Modular design of fully pipelined accumulators. FPT 2010: 118-125 - [c22]Jorge L. Ortiz, David Andrews:
A configurable high-throughput linear sorter system. IPDPS Workshops 2010: 1-8 - [c21]Miaoqing Huang, David Andrews, Jason Agron:
Operating System Structures for Multiprocessor Systems on Programmable Chip. ReConFig 2010: 358-363 - [e1]Toomas P. Plaks, David Andrews, Ronald F. DeMara, Herman Lam, Jooheung Lee, Christian Plessl, Greg Stitt:
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA. CSREA Press 2010, ISBN 1-60132-140-6 [contents]
2000 – 2009
- 2009
- [c20]Jason Agron, David Andrews:
Building heterogeneous reconfigurable systems with a hardware microkernel. CODES+ISSS 2009: 393-402 - [c19]Jason Agron, David Andrews:
Building heterogeneous reconfigurable systems using threads. FPL 2009: 435-438 - [c18]Jason Agron, David Andrews:
Hardware Microkernels for Heterogeneous Manycore Systems. ICPP Workshops 2009: 19-26 - 2008
- [j7]David Andrews, Ron Sass, Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp:
Achieving Programming Model Abstractions for Reconfigurable Computing. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 34-44 (2008) - [c17]Shane Santner, Wesley Peck, Jason Agron, David Andrews:
Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs. ARC 2008: 99-110 - [c16]Elias Teodoro Silva Jr., David Andrews, Carlos Eduardo Pereira, Flávio Rech Wagner:
An Infrastructure for Hardware-Software Co-Design of Embedded Real-Time Java Applications. ISORC 2008: 273-280 - 2007
- [c15]Erik K. Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David L. Andrews:
Memory Hierarchy for MCSoPC Multithreaded Systems. ERSA 2007: 44-50 - [c14]Erik K. Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David Andrews:
Supporting High Level Language Semantics Within Hardware Resident Threads. FPL 2007: 98-103 - 2006
- [c13]David L. Andrews, Ron Sass, Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp:
The Case for High Level Programming Models for Reconfigurable Computers. ERSA 2006: 21-32 - [c12]Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David Andrews:
Enabling a Uniform Programming Model Across the Software/Hardware Boundary. FCCM 2006: 89-98 - [c11]Wesley Peck, Erik K. Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, David Andrews:
Hthreads: A Computational Model for Reconfigurable Devices. FPL 2006: 1-4 - [c10]Jason Agron, Wesley Peck, Erik K. Anderson, David Andrews, Ed Komp, Ron Sass, Fabrice Baijot, Jim Stevens:
Run-Time Services for Hybrid CPU/FPGA Systems on Chip. RTSS 2006: 3-12 - 2005
- [c9]Razali Jidin, David Andrews, Wesley Peck, Dan Chirpich, Kevin Stout, John M. Gauch:
Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms. IPDPS 2005 - 2004
- [j6]David Andrews, Douglas Niehaus, Peter J. Ashenden:
Programming Models for Hybrid CPU/FPGA Chips. Computer 37(1): 118-120 (2004) - [j5]David Andrews, Douglas Niehaus, Razali Jidin, Michael Finley, Wesley Peck, Michael Frisbie, Jorge L. Ortiz, Ed Komp, Peter J. Ashenden:
Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link. IEEE Micro 24(4): 42-53 (2004) - 2003
- [c8]David Andrews, Joe Evans, Venumadhav Mangipudi, Aditya Mandapaka:
SCIMPS: An Integrated Approach to Distributed Processing in Sensor Webs. IPDPS 2003: 111 - [c7]David Andrews, Douglas Niehaus:
Architectural Frameworks for MPP Systems on a Chip. IPDPS 2003: 265 - [c6]Douglas Niehaus, David Andrews:
Using the Multi-Threaded Computation Model as a Unifying Framework for Hardware-Software Co-Design and Implementation. WORDS Fall 2003: 317-324 - 2002
- [j4]David Andrews, Paul Austin, Peter Costello, David O. LeVan:
Interprocess communications in the AN/BSY-2 distributed computer system: a case study. J. Syst. Softw. 61(3): 233-242 (2002) - [j3]David L. Andrews, Ravi Vemuri, David M. Chelberg, David Fleeman, David Parrott, Lonnie R. Welch, Scott A. Brandt:
A Framework for using benefit functions in complex real-time systems. Parallel Distributed Comput. Pract. 5(1) (2002) - [c5]David Andrews, Lonnie R. Welch, David M. Chelberg, Scott A. Brandt:
A Framework for Using Benefit Functions In Complex Real Time Systems. IPDPS 2002
1990 – 1999
- 1998
- [c4]David L. Andrews, Mitchell A. Thornton:
Integration of CAD tools and structured design principles in an undergraduate computer engineering curriculum. WCAE@ISCA 1998: 21 - 1997
- [j2]William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg:
Seeking Solutions in Configurable Computing. Computer 30(12): 38-43 (1997) - [c3]Mitchell A. Thornton, David L. Andrews:
Graph Analysis and Transformation Techniques for Runtime Minimization in Multi-Threaded Architectures. HICSS (1) 1997: 566-575 - 1995
- [c2]David L. Andrews, Andrew Wheeler, Barry Wealand, Cliff Kancler:
Rapid prototype of a hardware emulator for a SIMD processor array. ED&TC 1995: 391-397 - 1994
- [c1]David L. Andrews, Andrew Wheeler, Barry Wealand, Cliff Kancler:
Rapid prototype of an SIMD processor array (using FPGA's). RSP 1994: 28-33 - 1991
- [j1]Daniel Pease, Arif Ghafoor, Ishfaq Ahmad, David L. Andrews, Kamal Foudil-Bey, Thomas E. Karpinski, Mohammad A. Mikki, Mohamed Zerrouki:
PAWS: A Performance Evaluation Tool for Parallel Computing Systems. Computer 24(1): 18-29 (1991)
Coauthor Index
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