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ORCIDTsutomu Yoshihara
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2010 – 2019
- 2016
[j28]Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara:
Design of a Sensorless Controller Synthesized by Robust H∞ Control for Boost Converters. IEICE Trans. Commun. 99-B(2): 356-363 (2016)- 2013
- [j27]Hao Zhang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara:
Self-Cascode MOSFET with a Self-Biased Body Effect for Ultra-Low-Power Voltage Reference Generator. IEICE Trans. Electron. 96-C(6): 859-866 (2013) - [j26]Kazuhiro Ueda, Fukashi Morishita
, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto:
Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. IEEE J. Solid State Circuits 48(11): 2608-2617 (2013) - 2012
- [j25]Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara:
An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 439-446 (2012) - [c9]Jingyang Li, Yimeng Zhang, Tsutomu Yoshihara:
A novel charge recovery logic structure with complementary pass-transistor network. ISOCC 2012: 17-20 - [c8]Ning Ren, Hao Zhang, Tsutomu Yoshihara:
A CMOS voltage reference combining body effect with switched-current technique. ISOCC 2012: 92-95 - [c7]Luchen Yu, Yuan Zhu, Minjie Chen, Tsutomu Yoshihara:
High efficiency multi-channel LED driver based on SIMO switch-mode converter. ISOCC 2012: 483-486 - 2011
- [j24]Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara:
An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic. IEICE Trans. Electron. 94-C(4): 605-612 (2011) - [j23]Mengshu Huang, Leona Okamura, Tsutomu Yoshihara:
An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Non-volatile Memory. IEICE Trans. Electron. 94-C(6): 968-976 (2011) - [c6]Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara:
A non-rectifier wireless power transmission system using on-chip inductor. ASICON 2011: 112-115 - [c5]Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara:
Double charge pump circuit with triple charge sharing clock scheme. ASICON 2011: 128-132 - [c4]Chong Zhang, Tsutomu Yoshihara:
Word error control algorithm through multi-reading for NAND Flash memories. ASICON 2011: 236-239 - [c3]Hao Zhang, Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara:
CMOS low-power subthreshold reference voltage utilizing self-biased body effect. ASICON 2011: 516-519 - [c2]Yimeng Zhang, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara:
A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic. A-SSCC 2011: 213-216 - [c1]Jiemin Zhou, Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara:
A novel charge sharing charge pump for energy harvesting application. ISOCC 2011: 373-376
2000 – 2009
- 2008
- [j22]Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits 43(1): 96-108 (2008) - 2007
- [j21]Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits 42(4): 820-829 (2007) - 2005
- [j20]Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara:
Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories. IEICE Trans. Electron. 88-C(2): 255-263 (2005) - [j19]Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. 88-C(4): 622-629 (2005) - [j18]Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara:
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. 88-C(10): 2020-2027 (2005) - [j17]Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits 40(1): 204-212 (2005) - [j16]Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40(1): 245-253 (2005) - 2004
- [j15]Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara:
A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. IEEE J. Solid State Circuits 39(1): 194-206 (2004) - 2001
- [j14]Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara:
Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits 36(1): 46-54 (2001) - [j13]Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba:
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. IEEE J. Solid State Circuits 36(2): 249-257 (2001) - 2000
- [j12]Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara:
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits 35(5): 751-756 (2000) - [j11]Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara:
High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits 35(8): 1169-1178 (2000) - [j10]Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki:
A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs. IEEE J. Solid State Circuits 35(8): 1179-1185 (2000) - [j9]Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara:
A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE J. Solid State Circuits 35(11): 1680-1689 (2000)
1990 – 1999
- 1994
- [j8]Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara:
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. IEEE J. Solid State Circuits 29(4): 454-460 (1994) - [j7]Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara:
An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits 29(11): 1303-1309 (1994) - [j6]Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara:
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. IEEE J. Solid State Circuits 29(11): 1323-1329 (1994)
1980 – 1989
- 1989
- [j5]Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara:
Twisted bit-line architectures for multi-megabit DRAMs. IEEE J. Solid State Circuits 24(1): 21-27 (1989) - [j4]Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara:
Analysis of coupling noise between adjacent bit lines in megabit DRAMs. IEEE J. Solid State Circuits 24(1): 35-42 (1989) - [j3]Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara:
A 5 V only one-transistor 256 K EEPROM with page-mode erase. IEEE J. Solid State Circuits 24(4): 911-915 (1989) - [j2]Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara:
120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs. IEEE J. Solid State Circuits 24(5): 1244-1249 (1989) - 1988
- [j1]Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara:
A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM. IEEE J. Solid State Circuits 23(1): 86-90 (1988)
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