"A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data ..."

Fukashi Morishita et al. (2005)

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DOI: 10.1109/JSSC.2004.837986

access: closed

type: Journal Article

metadata version: 2023-06-26

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Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits 40(1): 204-212 (2005)

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