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ORCIDYasunobu Nakase
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2010 – 2019
- 2014
[c5]Ryota Yasudo
, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura:
A low power NoC router using the marching memory through type. COOL Chips 2014: 1-3- [c4]Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura:
Design of a low power NoC router using Marching Memory Through type. NOCS 2014: 111-118 - 2013
- [j11]Yasunobu Nakase, Yasuhiro Ido, Tsukasa Oishi, Toru Shimizu:
On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes. IEICE Trans. Electron. 96-C(11): 1420-1427 (2013) - [j10]Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu:
0.5 V Start-Up 87% Efficiency 0.75 mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration. IEEE J. Solid State Circuits 48(8): 1933-1942 (2013) - 2012
- [c3]Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu:
A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration. CICC 2012: 1-4 - 2011
- [c2]Yasunobu Nakase, Shinichi Hirose, Toru Goda, Kehui Hu, Hiroshi Onoda, Yasuhiro Ido, Hiroyuki Kondo, Wei Kong, Wei Zhang, Tsukasa Oishi, Shintaro Mori, Toru Shimizu:
0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers. A-SSCC 2011: 21-24
2000 – 2009
- 2001
- [j9]Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba:
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. IEEE J. Solid State Circuits 36(2): 249-257 (2001)
1990 – 1999
- 1999
- [j8]Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada:
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34(4): 494-501 (1999) - 1997
- [j7]Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits 32(2): 292 (1997) - [j6]Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko:
Authors Reply. IEEE J. Solid State Circuits 32(2): 293 (1997) - 1996
- [j5]Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits 31(4): 504-513 (1996) - [j4]Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko:
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits 31(6): 773-783 (1996) - [j3]Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits 31(8): 1157-1164 (1996) - 1995
- [j2]Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko:
A BiCMOS wired-OR logic. IEEE J. Solid State Circuits 30(6): 622-628 (1995) - 1993
- [c1]Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara:
A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. ICCD 1993: 202-205
1980 – 1989
- 1988
- [j1]Yasunobu Nakase, Kenji Anami, Tohru Shiomi, Atsushi Ohba, Shinpei Kayano:
A macro analysis of soft errors in static RAMs. IEEE J. Solid State Circuits 23(2): 604-605 (1988)
Coauthor Index
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