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"An 8.8-ns 54×54-bit multiplier with high speed redundant binary ..."

Hiroshi Makino et al. (1996)

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DOI: 10.1109/4.509863

access: closed

type: Journal Article

metadata version: 2022-07-26

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  - https://dblp.org/rec/journals/jssc/MakinoNSMSM96
Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko:
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits 31(6): 773-783 (1996)

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