"Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM ..."

Yasunobu Nakase et al. (1999)

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DOI: 10.1109/4.753682

access: closed

type: Journal Article

metadata version: 2022-07-05

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Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada:
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34(4): 494-501 (1999)

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