"Leading-zero anticipatory logic for high-speed floating point addition."

Hiroaki Suzuki et al. (1996)

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DOI: 10.1109/4.508263

access: closed

type: Journal Article

metadata version: 2022-07-18

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  - https://dblp.org/rec/journals/jssc/SuzukiMMNMS96
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits 31(8): 1157-1164 (1996)

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