default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVojin G. Oklobdzija
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2010 – 2019
- 2015
[c50]Mustafa Aktan, Dursun Baran
, Vojin G. Oklobdzija:
Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders. ARITH 2015: 10-17- 2011
- [c49]Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija:
Multiplier structures for low power applications in deep-CMOS. ISCAS 2011: 1061-1064 - [c48]Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija:
A Quick Method for Energy Optimized Gate Sizing of Digital Circuits. PATMOS 2011: 1-10 - 2010
- [j31]Hossein Karimiyan Alidash, Vojin G. Oklobdzija:
Low-Power Soft Error Hardened Latch. J. Low Power Electron. 6(1): 218-226 (2010) - [j30]Bart R. Zeydel, Dursun Baran, Vojin G. Oklobdzija:
Energy-Efficient Design Methodologies: High-Performance VLSI Adders. IEEE J. Solid State Circuits 45(6): 1220-1233 (2010) - [c47]Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija:
Energy efficient implementation of parallel CMOS multipliers with improved compressors. ISLPED 2010: 147-152 - [c46]Vojin G. Oklobdzija:
Computing at the ultimate low-energy limits. SBCCI 2010: 1 - [c45]Lei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija:
Design of a link-controller architecture for multiple serial link protocols. SoCC 2010: 266-271 - [e3]Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim:
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. ACM 2010, ISBN 978-1-4503-0146-6 [contents]
2000 – 2009
- 2009
- [c44]Hossein Karimiyan Alidash, Vojin G. Oklobdzija:
Low-Power Soft Error Hardened Latch. PATMOS 2009: 256-265 - [c43]Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija:
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). PATMOS 2009: 307-316 - 2008
- [j29]Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija:
Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(10): 3038-3049 (2008) - [c42]Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija:
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. PATMOS 2008: 268-276 - [p1]Vojin G. Oklobdzija:
Reduced Instruction Set Computing. Wiley Encyclopedia of Computer Science and Engineering 2008 - [e2]Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle:
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008. ACM 2008, ISBN 978-1-60558-109-5 [contents] - 2007
- [j28]Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija:
The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements. IEEE J. Solid State Circuits 42(6): 1392-1404 (2007) - [c41]Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija:
Logic Style Comparison for Ultra Low Power Operation in 65nm Technology. PATMOS 2007: 181-190 - 2006
- [j27]Steven K. Hsu, Sanu K. Mathew, Mark A. Anders, Bart R. Zeydel, Vojin G. Oklobdzija, Ram K. Krishnamurthy, Shekhar Y. Borkar:
A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS. IEEE J. Solid State Circuits 41(1): 256-264 (2006) - [j26]Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija:
Energy optimization of pipelined digital systems using circuit sizing and supply scaling. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 122-134 (2006) - [c40]Xiao Yan Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija:
Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. PATMOS 2006: 47-55 - [c39]Bart R. Zeydel, Vojin G. Oklobdzija:
Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations. PATMOS 2006: 127-136 - [c38]Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija:
Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. PATMOS 2006: 148-156 - [c37]Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija:
Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. PATMOS 2006: 360-369 - 2005
- [j25]Nikola Nedovic, Vojin G. Oklobdzija:
Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Trans. Very Large Scale Integr. Syst. 13(5): 577-590 (2005) - [j24]Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy:
Comparison of high-performance VLSI adders in the energy-delay space. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 754-758 (2005) - [c36]Bart R. Zeydel, Theo T. J. H. Kluter, Vojin G. Oklobdzija:
Efficient Mapping of Addition Recurrence Algorithms in CMOS. IEEE Symposium on Computer Arithmetic 2005: 107-113 - [c35]Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija:
Architectural Considerations for Energy Efficiency. ICCD 2005: 13-16 - [c34]Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija:
Low- and Ultra Low-Power Arithmetic Units: Design and Comparison. ICCD 2005: 249-252 - [c33]Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija:
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS 2005: 724-732 - [e1]Vojin G. Oklobdzija:
Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, Marina del Rey, CA, USA, October 24-26, 2005. IASTED/ACTA Press 2005, ISBN 0-88986-509-4 [contents] - 2004
- [j23]Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija:
A test circuit for measurement of clocked storage element characteristics. IEEE J. Solid State Circuits 39(8): 1294-1304 (2004) - 2003
- [j22]Vojin G. Oklobdzija:
Clocking and clocked storage elements in a multi-gigahertz environment. IBM J. Res. Dev. 47(5-6): 567-584 (2003) - [c32]Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy:
Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. IEEE Symposium on Computer Arithmetic 2003: 272-279 - [c31]Vojin G. Oklobdzija, Ram Krishnamurthy:
Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs. IEEE Symposium on Computer Arithmetic 2003: 280 - [c30]Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija:
Energy minimization method for optimal energy-delay extraction. ESSCIRC 2003: 177-180 - [c29]Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait:
Area-time optimal adder with relative placement generator. ISCAS (5) 2003: 141-144 - [c28]Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker:
An efficient transistor optimizer for custom circuits. ISCAS (5) 2003: 197-200 - [c27]Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija:
Energy Optimization of High-Performance Circuits. PATMOS 2003: 399-408 - 2002
- [c26]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Comparative analysis of double-edge versus single-edge triggered clocked storage elements. ISCAS (5) 2002: 105-108 - [c25]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Conditional pre-charge techniques for power-efficient dual-edge clocking. ISLPED 2002: 56-59 - [c24]Vojin G. Oklobdzija, Jens Sparsø:
Future directions in clocking multi-ghz systems. ISLPED 2002: 219 - [c23]Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan:
Optimal Sequencing Energy Allocation for CMOS Integrated Systems. ISQED 2002: 194-199 - [c22]Hoang Q. Dao, Vojin G. Oklobdzija:
Performance Comparison of VLSI Adders Using Logical Effort. PATMOS 2002: 25-34 - [c21]Vojin G. Oklobdzija:
Clocking and Clocked Storage Elements in Multi-GHz Environment. PATMOS 2002: 128-145 - 2001
- [c20]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Timing Characterization of Dual-edge Triggered Flip-flops. ICCD 2001: 538-541 - [c19]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Conditional techniques for low power consumption flip-flops. ICECS 2001: 803-806 - [c18]Hoang Q. Dao, Kevin J. Nowka, Vojin G. Oklobdzija:
Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation. ISLPED 2001: 56-59 - 2000
- [j21]Borivoje Nikolic, Vojin G. Oklobdzija, Vladimir Stojanovic, Wenyan Jia, James Kar-Shing Chiu, Michael Ming-Tak Leung:
Improved sense-amplifier-based flip-flop: design and measurements. IEEE J. Solid State Circuits 35(6): 876-884 (2000) - [j20]Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current:
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 460-463 (2000) - [c17]Nikola Nedovic, Vojin G. Oklobdzija:
Dynamic Flip-Flop with Improved Power. ICCD 2000: 323-326 - [c16]Aamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija:
Partitioned Branch Condition Resolution Logic. SBCCI 2000: 35-40 - [c15]Nikola Nedovic, Vojin G. Oklobdzija:
Hybrid latch Flip-Flop with Improved Power Efficiency. SBCCI 2000: 211-215
1990 – 1999
- 1999
- [j19]Vladimir Stojanovic, Vojin G. Oklobdzija:
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE J. Solid State Circuits 34(4): 536-548 (1999) - [c14]Aamir A. Farooqui, Vojin G. Oklobdzija:
VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing. Great Lakes Symposium on VLSI 1999: 30-33 - 1998
- [j18]Paul F. Stelling, Charles U. Martel, Vojin G. Oklobdzija, R. Ravi:
Optimal Circuits for Parallel Multipliers. IEEE Trans. Computers 47(3): 273-285 (1998) - [c13]Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa:
Comparative analysis of latches and flip-flops for high-performance systems. ICCD 1998: 264-269 - [c12]Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa:
A unified approach in the analysis of latches and flip-flops for low-power systems. ISLPED 1998: 227-232 - 1997
- [j17]Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits 32(2): 292 (1997) - [c11]Paul F. Stelling, Vojin G. Oklobdzija:
Implementing Multiply-Accumulate Operation in Multiplication Time. IEEE Symposium on Computer Arithmetic 1997: 99- - [c10]Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current:
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. ISLPED 1997: 323-327 - 1996
- [j16]Vojin G. Oklobdzija:
An ECL gate with improved speed and low power in a BiCMOS process. IEEE J. Solid State Circuits 31(1): 77-83 (1996) - [j15]Vojin G. Oklobdzija, David Villeger, Simon S. Liu:
A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach. IEEE Trans. Computers 45(3): 294-306 (1996) - [j14]Vojin G. Oklobdzija, Belle Wei:
Guest editors' introduction. J. VLSI Signal Process. 14(3): 239-240 (1996) - [j13]Richard H. Strandberg, Luis G. Bustamante, Vojin G. Oklobdzija, Michael A. Soderstrand, Jean-Claude Duc:
Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters. J. VLSI Signal Process. 14(3): 303-309 (1996) - [j12]Paul F. Stelling, Vojin G. Oklobdzija:
Design strategies for optimal hybrid final adders in a parallel multiplier. J. VLSI Signal Process. 14(3): 321-331 (1996) - [c9]K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic:
Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. ISMVL 1996: 86-91 - 1995
- [j11]Richard Scalettar, K. J. Runge, J. Correa, P. Lee, Vojin G. Oklobdzija, J. L. Vujic:
Simulations of Interacting Many Body Systems Using P4. Int. J. High Speed Comput. 7(3): 327-349 (1995) - [j10]Mikhail N. Dorojevets, Vojin G. Oklobdzija:
Multithreaded Decoupled Architecture. Int. J. High Speed Comput. 7(3): 465-480 (1995) - [j9]Vojin G. Oklobdzija, David Villeger:
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 292-301 (1995) - [c8]Charles U. Martel, Vojin G. Oklobdzija, R. Ravi, Paul F. Stelling:
Design Strategies for Optimal Multiplier Circuits. IEEE Symposium on Computer Arithmetic 1995: 42-49 - [c7]K. J. Runge, L. P. Lee, J. Correa, Richard Scalettar, Vojin G. Oklobdzija:
Monte Carlo and molecular dynamics simulations using p4. IPPS 1995: 53-59 - 1994
- [j8]Vojin G. Oklobdzija:
An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 124-128 (1994) - [j7]Vojin G. Oklobdzija, David Villeger, Thierry Soulas:
An integrated multiplier for complex numbers. J. VLSI Signal Process. 7(3): 213-222 (1994) - [c6]Vojin G. Oklobdzija:
High-Performance Computer Arithmetic and Implementations: Introduction. HICSS (1) 1994: 280-281 - [c5]Rupinder Hundal, Vojin G. Oklobdzija:
Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination. ICCD 1994: 60-64 - 1992
- [j6]Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija:
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. IEEE Trans. Computers 41(8): 920-930 (1992) - 1991
- [j5]Vojin G. Oklobdzija, Belle Wei:
Introduction. J. VLSI Signal Process. 3(4): 263 (1991) - [j4]Brian D. Lee, Vojin G. Oklobdzija:
Improved CLA scheme with optimized delay. J. VLSI Signal Process. 3(4): 265-274 (1991) - [c4]Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija:
Delay optimization of carry-skip adders and block carry-lookahead adders. IEEE Symposium on Computer Arithmetic 1991: 154-164
1980 – 1989
- 1988
- [j3]Vojin G. Oklobdzija, Earl R. Barnes:
On Implementing Addition in VLSI Technology. J. Parallel Distributed Comput. 5(6): 716-728 (1988) - [j2]Vojin G. Oklobdzija:
Issues in CPU-coprocessor communication and synchronization. Microprocess. Microprogramming 24(1-5): 695-700 (1988) - [c3]N. M. Marinovic, Vojin G. Oklobdzija, L. Roytman:
VLSI architecture of a real-time Wigner distribution processor for acoustic signals. ICASSP 1988: 2112-2115 - 1985
- [c2]Vojin G. Oklobdzija, Earl R. Barnes:
Some optimal schemes for ALU implementation in VLSI technology. IEEE Symposium on Computer Arithmetic 1985: 2-8 - 1984
- [c1]J. Paul Roth, Vojin G. Oklobdzija, John F. Beetem:
Test Generation for FET Switching Circuits. ITC 1984: 59-62 - 1982
- [j1]Vojin G. Oklobdzija, Milos D. Ercegovac:
A On-Line Square Root Algorithm. IEEE Trans. Computers 31(1): 70-75 (1982)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 22:07 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
