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ORCID16th PATMOS 2006: Montpellier, France
- Johan Vounckx, Nadine Azémard, Philippe Maurine:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings. Lecture Notes in Computer Science 4148, Springer 2006, ISBN 3-540-39094-4
High-Level Design
- Anatoly Prihozhy
, Daniel Mlynek:
Design of Parallel Implementations by Means of Abstract Dynamic Critical Path Based Profiling of Complex Sequential Algorithms. 1-11 - Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest:
Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism. 12-23 - Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak:
Handheld System Energy Reduction by OS-Driven Refresh. 24-35
Power Estimation / Modeling
- Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri:
Delay Constrained Register Transfer Level Dynamic Power Estimation. 36-46 - Xiao Yan Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija:
Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. 47-55 - Domenik Helms, Marko Hoyer, Wolfgang Nebel:
Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. 56-65 - José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura:
Leakage Power Characterization Considering Process Variations. 66-74
Memory and Register Files
- Abel G. Silva-Filho, Filipe R. Cordeiro, Remy Eskinazi Sant'Anna, Manoel Eusébio de Lima:
Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance. 75-83 - Hanene Ben Fradj, Cécile Belleudy, Michel Auguin:
System Level Multi-bank Main Memory Configuration for Energy Reduction. 84-94 - Ka-Ming Keung, Akhilesh Tyagi:
SRAM CP: A Charge Recycling Design Schema for SRAM. 95-106 - David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo:
Compiler-Driven Leakage Energy Reduction in Banked Register Files. 107-116
Low-Power Digital Circuits
- M. Hillers, Wolfgang Nebel:
Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits. 117-126 - Bart R. Zeydel, Vojin G. Oklobdzija:
Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations. 127-136 - Stefan Cserveny:
Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage Regulator. 137-147 - Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija:
Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. 148-156
Busses and Interconnects
- Philippe Grosse, Yves Durand, Paul Feautrier:
Power Modeling of a NoC Based Design for High Speed Telecommunication Systems. 157-168 - Tudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner:
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. 169-180 - Kenichi Okada, Takumi Uezono, Kazuya Masu:
Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. 181-190 - Abbas Sheibanyrad, Alain Greiner:
Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. 191-202
Low Power Techniques
- Theodoros Giannopoulos, Vassilis Paliouras:
Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters. 203-213 - Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino:
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. 214-224 - Toshiro Akino, Takashi Hamahata:
A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation. 225-236 - B. Chung, J. B. Kuo:
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. 237-246
Applications and SoC Design
- Tiago Dias, Nuno Roma, Leonel Sousa:
Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators. 247-255 - Gurhan Kucuk, Can Basaran:
Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCache. 256-266 - Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez:
A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus. 267-279 - Julien Mercier, Christian Dufaza, Mathieu Lisart:
Methodology for Dynamic Power Verification of Contactless Smartcards. 280-291 - Jong-Pil Son, Kyu-Young Kim, Ji-Yong Jeong, Yogendera Kumar, Soo-Won Kim:
New Battery Status Checking Method for Implantable Biomedical Applications. 292-300
Modeling
- Daniel Lima Ferrão, Ricardo Reis, José Luís Almada Güntzel:
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. 301-310 - Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. 311-318 - Christophe Alexandre, Marek Sroka, Hugo Clément, Christian Masson:
Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow. 319-328 - Mini Nanua, David T. Blaauw:
Receiver Modeling for Static Functional Crosstalk Analysis. 329-339 - Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
Modeling of Crosstalk Fault in Defective Interconnects. 340-349
Digital Circuits
- Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim:
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits. 350-359 - Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija:
Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. 360-369 - Hai Lin, Yu Wang, Rong Luo, Huazhong Yang, Hui Wang:
IR-drop Reduction Through Combinational Circuit Partitioning. 370-381 - Jianping Hu, Hong Li, Yangbo Wu:
Low-Power Register File Based on Adiabatic Logic Circuits. 382-392 - Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa:
High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI. 393-402
Reconfigurable and Programmable Devices
- Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis:
Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. 403-414 - David Elléouet, Yannig Savary, Nathalie Julien:
An FPGA Power Aware Design Flow. 415-424 - Yijun Liu, Steve B. Furber, Zhenkun Li:
The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing. 425-438
Poster 1
- Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta:
Optimization of Master-Slave Flip-Flops for High-Performance Applications. 439-449 - Benjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod:
Hierarchical Modeling of a Fractional Phase Locked Loop. 450-457 - Régis Roubadia, Sami Ajram, Guy Cathébras:
Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs. 458-467 - V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine:
Statistical Characterization of Library Timing Performance. 468-476 - Oguz Ergin:
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors. 477-485 - Saihua Lin, Hongli Gao, Huazhong Yang:
Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS. 486-495 - Jürgen Rauscher, Hans-Jörg Pfleiderer:
Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations. 496-503 - Saihua Lin, Huazhong Yang:
Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling. 504-513
Poster 2
- Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López:
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. 514-523 - Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo:
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. 524-531 - Davide Pandini, Guido A. Repetto:
Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design. 532-542 - Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu:
A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. 543-552 - Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu:
Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors. 553-562 - Clemens Schlachta, Manfred Glesner:
A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages. 563-572 - Diganchal Chakraborty, P. P. Chakrabarti, Arijit Mondal, Pallab Dasgupta:
A Framework for Estimating Peak Power in Gate-Level Circuits. 573-582
Poster 3
- Eslam Yahya, Marc Renaudin:
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. 583-592 - Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. 593-602 - José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis:
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. 603-613 - Preetham Lakshmikanthan, Adrian Nunez:
A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits. 614-623 - Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. 624-633 - Alin Razafindraibe, Michel Robert, Philippe Maurine:
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. 634-644 - Felipe Machado, Teresa Riesgo, Yago Torroja:
A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. 645-657
Keynotes
- Giovanni De Micheli:
Nanoelectronics: Challenges and Opportunities. 658 - Christian Piguet, Christian Schuster, Jean-Luc Nagel:
Static and Dynamic Power Reduction by Architecture Selection. 659-668 - Peter A. Beerel:
Asynchronous Design for High-Speed and Low-Power Circuits. 669 - Robin Wilson:
Design for Volume Manufacturing in the Deep Submicron ERA. 670
Industrial Session
- Francesco Pessolano:
The Holy Grail of Holistic Low-Power Design. 671 - Jean Oudinot:
Top Verification of Low Power System with "Checkerboard" Approach. 672 - Francois Thomas:
The Power Forward Initiative. 673
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