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ORCIDRaghuram S. Tupuri
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2000 – 2009
- 2008
[c9]Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri:
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. VLSI Design 2008: 521-526- 2006
- [c8]Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri:
Delay Constrained Register Transfer Level Dynamic Power Estimation. PATMOS 2006: 36-46 - 2003
- [j1]Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri:
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. J. Electron. Test. 19(2): 149-160 (2003) - 2002
- [c7]Jacob A. Abraham, Arun Krishnamachary, Raghuram S. Tupuri:
A Comprehensive Fault Model for Deep Submicron Digital Circuits. DELTA 2002: 360-364 - 2001
- [c6]Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri:
Timing Verification and Delay Test Generation for Hierarchical Designs. VLSI Design 2001: 157-162 - 2000
- [c5]Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab:
Hierarchical Test Generation for Systems On a Chip. VLSI Design 2000: 198-
1990 – 1999
- 1999
- [c4]Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham:
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. DAC 1999: 647-652 - 1997
- [c3]Raghuram S. Tupuri, Jacob A. Abraham:
A Novel Functional Test Generation Method for Processors Using Commercial ATPG. ITC 1997: 743-752 - [c2]Raghuram S. Tupuri, Jacob A. Abraham:
A Novel Hierarchical Test Generation Method for Processors. VLSI Design 1997: 540-541 - 1992
- [c1]Soumitra De Sirkar, Raghuram S. Tupuri, C. Sudha Madhuri, G. Rajagopalan, Kalpesh D. Mehta, C. G. Madhukar, Giridhar Bajpe:
Design Migration Across Technology - Making It Work. VLSI Design 1992: 68-72
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