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Guadalupe Miñana
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2020 – today
- 2024
- [i1]Marcos Sánchez-Élez, Inmaculada Pardines, Pablo García, Guadalupe Miñana, Sara Román Navarro, Margarita Sánchez, José L. Risco-Martín:
Enhancing Students' Learning Process Through Self-Generated Tests. CoRR abs/2403.15488 (2024)
2010 – 2019
- 2013
- [c6]Victoria López, Matilde Santos Peñas, Guadalupe Miñana, Raquel Caro, Susanne Escobar-Torres Kraemmer, M. Sánchez Balmaseda, Guillermo Botella Juan:
Memories in Complutense Campus. A Tribute to Prof. Dr. Da Ruan 2013: 143-150
2000 – 2009
- 2007
- [j1]Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
, Oscar Garnica
, Sonia López:
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. IET Comput. Digit. Tech. 1(2): 113-119 (2007) - 2006
- [c5]José Manuel Colmenar, Oscar Garnica
, Juan Lanchares, José Ignacio Hidalgo
, Guadalupe Miñana, Sonia López:
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. DSD 2006: 423-432 - [c4]Guadalupe Miñana, Oscar Garnica
, José Ignacio Hidalgo
, Juan Lanchares, José Manuel Colmenar:
A Power-Aware Technique for Functional Units in High-Performance Processors. DSD 2006: 456-459 - [c3]José Manuel Colmenar, Oscar Garnica
, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López:
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par 2006: 495-505 - [c2]Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica
, Juan Lanchares, José Manuel Colmenar, Sonia López:
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. PATMOS 2006: 514-523 - 2005
- [c1]Guadalupe Miñana, Oscar Garnica
, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar:
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. PATMOS 2005: 40-48
Coauthor Index
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last updated on 2025-01-09 13:26 CET by the dblp team
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