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ORCIDKazunari Inoue
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2010 – 2019
- 2019
[c10]Kazunari Inoue, Nozomi Kobori, Atsushi Hirota, Tetsushi Koide, Takumi Okamoto:
An IoT-gateway with the information-centric communication. ISDCS 2019: 1-3- 2016
- [c9]Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka:
Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure. CCNC 2016: 309-314 - [c8]Kazunari Inoue, Yuji Yano:
A large scale access-control list for IoT security comprising embedded IP-core and DDR DRAM. ISOCC 2016: 197-198 - 2015
- [j11]Atsushi Ooka, Shingo Ata, Kazunari Inoue, Masayuki Murata
:
High-Speed Design of Conflictless Name Lookup and Efficient Selective Cache on CCN Router. IEICE Trans. Commun. 98-B(4): 607-620 (2015) - 2014
- [c7]Atsushi Ooka, Shingo Ata, Kazunari Inoue, Masayuki Murata:
Design of a high-speed content-centric-networking router using content addressable memory. INFOCOM Workshops 2014: 458-463 - 2013
- [j10]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue:
Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS. IEICE Trans. Commun. 96-B(7): 1819-1825 (2013) - [j9]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka:
A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application. IEICE Trans. Electron. 96-C(8): 1076-1082 (2013) - [j8]Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka:
A study on micro level traffic prediction for energy-aware routers. ACM SIGOPS Oper. Syst. Rev. 47(3): 26-33 (2013) - [c6]Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka:
2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving. CCNC 2013: 97-105 - 2012
- [j7]Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka:
FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine. IEICE Trans. Commun. 95-B(7): 2306-2314 (2012) - [c5]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue:
Deterministic High Density Packet-Buffer System for Low Cost Network Systems. AINA 2012: 951-956 - [c4]Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki:
A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. CICC 2012: 1-4 - [c3]Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue:
A slice structure using the management of network traffic prediction for green IT. HPSR 2012: 250-255 - [c2]Sou Koyano, Shingo Ata, Ikuo Oka, Kazunari Inoue:
A High-Grained Traffic Prediction for Microseconds Power Control in Energy-Aware Routers. UCC 2012: 347-352 - 2010
- [j6]Haesung Hwang, Shingo Ata, Koji Yamamoto, Kazunari Inoue, Masayuki Murata:
A New TCAM Architecture for Managing ACL in Routers. IEICE Trans. Commun. 93-B(11): 3004-3012 (2010) - [c1]Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka:
Hardware implementation of fast forwarding engine using standard memory and dedicated circuit. ICECS 2010: 379-382
2000 – 2009
- 2005
- [j5]Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. 88-C(4): 622-629 (2005) - [j4]Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide:
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. 88-C(6): 1332-1342 (2005) - [j3]Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40(1): 245-253 (2005)
1990 – 1999
- 1995
- [j2]Kazunari Inoue, Hisashi Nakamura, Hiroyuki Kawai:
A 10 Mb frame buffer memory with Z-compare and A-blend units. IEEE J. Solid State Circuits 30(12): 1563-1568 (1995) - [j1]Masaki Kumanoya, Toshiyuki Ogawa, Kazunari Inoue:
Advances in DRAM interfaces. IEEE Micro 15(6): 30-36 (1995)
Coauthor Index
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