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2020 – today
- 2022
[c18]Yuji Yano, Hisashi Iwamoto, Takuma Yoshimura, Yoshihiro Nishida, Tatsuya Mori, Kiyotaka Komoku, Hidekuni Takao, Kazutami Arimoto:
28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. VLSI-DAT 2022: 1-4- 2020
- [j9]Kento Watanabe
, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors. IEICE Trans. Commun. 103-B(6): 645-652 (2020) - [c17]Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto:
An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. AICAS 2020: 305-309
2010 – 2019
- 2019
- [j8]Kento Watanabe, Shintaro Izumi, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-Noise Photoplethysmography Sensor Using Correlated Double Sampling for Heartbeat Interval Acquisition. IEEE Trans. Biomed. Circuits Syst. 13(6): 1552-1562 (2019) - [j7]Seiya Yoshida, Shintaro Izumi, Koichi Kajihara, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3896-3905 (2019) - [c16]Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto:
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC 2019: 267-270 - [c15]Seiya Yoshida, Shintaro Izumi, Yuki Nishikawa, Kento Watanabe, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Heartbeat Interval Error Compensation Method Using Multiple Linear Regression for Photoplethysmography Sensors. BioCAS 2019: 1-4 - [c14]Kana Sasai, Shintaro Izumi, Kento Watanabe, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit. IEEE SENSORS 2019: 1-4 - 2018
- [c13]Yuji Yano:
A 5-ms Error, 22-μA Photoplethysmography Sensor using Current Integration Circuit and Correlated Double Sampling. EMBC 2018: 5566-5569 - [c12]Yuki Nishikawa, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring. ISCAS 2018: 1-5 - [c11]Koichi Kajihara, Shintaro Izumi, Seiya Yoshida, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis. SiPS 2018: 199-204 - 2016
- [j6]Hideaki Furukawa, Hiroaki Harai, Yasuto Kuroda, Yuji Yano, Shoji Koyama:
Demonstration of 100 Gbps optical packet switching using header processor based on 48-bit longest prefix matching. Photonic Netw. Commun. 31(3): 483-492 (2016) - [c10]Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka:
Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure. CCNC 2016: 309-314 - [c9]Kazunari Inoue, Yuji Yano:
A large scale access-control list for IoT security comprising embedded IP-core and DDR DRAM. ISOCC 2016: 197-198 - 2014
- [c8]Yuji Yano, Tomonori Hashiyama, Junko Ichino, Shun'ichi Tano:
Behavior extraction from tweets using character N-gram models. FUZZ-IEEE 2014: 1273-1280 - 2013
- [j5]Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuji Yano, Tatsuhiro Gake, Takahiro J. Yamaguchi, Nobukazu Takai:
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. J. Electron. Test. 29(6): 879-892 (2013) - [j4]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue:
Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS. IEICE Trans. Commun. 96-B(7): 1819-1825 (2013) - [j3]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka:
A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application. IEICE Trans. Electron. 96-C(8): 1076-1082 (2013) - [j2]Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai:
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. IEEE J. Solid State Circuits 48(11): 2671-2680 (2013) - [j1]Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka:
A study on micro level traffic prediction for energy-aware routers. ACM SIGOPS Oper. Syst. Rev. 47(3): 26-33 (2013) - [c7]Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka:
2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving. CCNC 2013: 97-105 - 2012
- [c6]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue:
Deterministic High Density Packet-Buffer System for Low Cost Network Systems. AINA 2012: 951-956 - [c5]Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuta Arakawa, Daiki Hirabayashi, Yuji Yano, Tatsuhiro Gake, Nobukazu Takai, Takahiro J. Yamaguchi:
Multi-bit sigma-delta TDC architecture with self-calibration. APCCAS 2012: 671-674 - [c4]Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki:
A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. CICC 2012: 1-4 - [c3]Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue:
A slice structure using the management of network traffic prediction for green IT. HPSR 2012: 250-255
2000 – 2009
- 2004
- [c2]Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch:
Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. ASP-DAC 2004: 543-544 - 2003
- [c1]Tetsushi Koide, Hans Jürgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda:
A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. ASP-DAC 2003: 591-592
Coauthor Index
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