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"A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS ..."

Toru Nakura et al. (2000)

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DOI: 10.1109/4.841503

access: closed

type: Journal Article

metadata version: 2022-04-13

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Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara:
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits 35(5): 751-756 (2000)

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