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ORCIDMasaki Tsukude
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1990 – 1999
- 1998
[j9]Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada:
400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits 33(5): 770-778 (1998)- 1997
- [j8]Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada:
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits 32(3): 477-482 (1997) - [j7]Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto:
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. IEEE J. Solid State Circuits 32(11): 1721-1727 (1997) - 1996
- [j6]Shigehiro Kuge, Fukashi Morishita
, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto:
SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits 31(4): 586-591 (1996) - [j5]Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits 31(11): 1645-1655 (1996) - 1995
- [j4]Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto:
Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. IEEE J. Solid State Circuits 30(11): 1183-1188 (1995) - 1994
- [j3]Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara:
An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits 29(11): 1303-1309 (1994) - 1993
- [j2]Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima:
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. 10(2): 6-12 (1993) - 1992
- [c2]Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima:
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC 1992: 615-622
1980 – 1989
- 1989
- [j1]Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano:
A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. IEEE J. Solid State Circuits 24(5): 1184-1190 (1989) - [c1]Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima:
A New Array Architecture for Parallel Testing in VLSI Memories. ITC 1989: 322-326
Coauthor Index
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