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Journal Articles
- 1996
[j6]Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki:
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. IEEE J. Solid State Circuits 31(4): 575-585 (1996)- [j5]Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki:
Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs. IEEE J. Solid State Circuits 31(4): 592-601 (1996) - 1994
- [j4]Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima
, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima:
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. IEEE J. Solid State Circuits 29(4): 432-440 (1994) - [j3]Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara:
An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits 29(11): 1303-1309 (1994) - 1990
- [j2]Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima:
The cache DRAM architecture: a DRAM with an on-chip cache memory. IEEE Micro 10(2): 14-25 (1990) - 1989
- [j1]Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara:
Twisted bit-line architectures for multi-megabit DRAMs. IEEE J. Solid State Circuits 24(1): 21-27 (1989)
Coauthor Index
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