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2000 – 2009
- 2005
[j3]Takashi Nasuno, Yoshihisa Matsubara, Hiromasa Kobayashi, Akiyuki Minami, Eiichi Soda, Hiroshi Tsuda, Koichiro Tsujita, Wataru Wakamiya, Nobuyoshi Kobayashi:
Novel via Chain Structure for Failure Analysis at 65 nm-Node Fixing OPC Using Inner and Outer via Chain Dummy Patterns. IEICE Trans. Electron. 88-C(5): 796-803 (2005)
1990 – 1999
- 1992
- [j2]Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima:
A 34-ns 16-Mb DRAM with controllable voltage down-converter. IEEE J. Solid State Circuits 27(7): 1020-1027 (1992)
1980 – 1989
- 1989
- [j1]Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano:
A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. IEEE J. Solid State Circuits 24(5): 1184-1190 (1989)
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