"A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM."

Kunihiko Yamaguchi et al. (1992)

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DOI: 10.1109/4.127339

access: closed

type: Journal Article

metadata version: 2025-02-03

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Kunihiko Yamaguchi, Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Toshiro Hiramoto, Nobuo Tamba, Kunihiko Watanabe, Masanori Odaka, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai:
A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM. IEEE J. Solid State Circuits 27(2): 167-174 (1992)

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