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ORCIDYouji Idei
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1990 – 1999
- 1998
[j3]Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana:
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register. IEEE J. Solid State Circuits 33(2): 253-259 (1998)- 1996
- [j2]Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta:
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. IEEE J. Solid State Circuits 31(10): 1443-1450 (1996) - 1995
- [j1]Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma:
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. IEEE J. Solid State Circuits 30(4): 491-499 (1995)
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