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ORCIDKatsuhiro Shimohigashi
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1990 – 1999
- 1998
[j5]Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana:
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register. IEEE J. Solid State Circuits 33(2): 253-259 (1998)
1980 – 1989
- 1989
- [j4]Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo:
A 9-ns 1-Mbit CMOS SRAM. IEEE J. Solid State Circuits 24(5): 1219-1225 (1989) - [j3]Makoto Suzuki, Suguru Tachibana, Atsuo Watanabe, Shoji Shukuri, Hisayuki Higuchi, Takahiro Nagano, Katsuhiro Shimohigashi:
A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM. IEEE J. Solid State Circuits 24(5): 1233-1237 (1989) - [j2]Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Atsuo Watnabe, Shoji Shukuri, Katsuhiro Shimohigashi:
A feedback-type BiCMOS logic gate. IEEE J. Solid State Circuits 24(5): 1360-1362 (1989) - 1988
- [j1]Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi:
An experimental large-capacity semiconductor file memory using 16-levels/cell storage. IEEE J. Solid State Circuits 23(1): 27-33 (1988)
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