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2020 – today
- 2020
[c5]Lei Sha, Anna Kuwana, Masashi Horiguchi, Haruo Kobayashi:
Simple Reference Voltage Generation Circuit Insensitive to Temperature. ISOCC 2020: 242-243
2010 – 2019
- 2012
- [c4]Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi, Moriyoshi Ota:
A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from -50°C to +150°C using piecewise-linear-current curvature compensation. VLSIC 2012: 22-23 - 2011
- [b2]Masashi Horiguchi, Kiyoo Itoh:
Nanoscale Memory Repair. Integrated Circuits and Systems, Springer 2011, ISBN 978-1-4419-7957-5, pp. 1-215 - [c3]Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi:
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC 2011: 1-7
2000 – 2009
- 2007
- [b1]Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka:
Ultra-Low Voltage Nano-Scale Memories. Series on Integrated Circuits and Systems, Springer 2007, ISBN 978-0-387-33398-4, pp. 1-346 - [c2]Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka:
Low-voltage limitations of memory-rich nano-scale CMOS LSIs. ESSCIRC 2007: 68-75 - 2006
- [c1]Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara:
Ultra-low voltage nano-scale embedded RAMs. ISCAS 2006 - 2003
- [j8]Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara
, Kiyoo Itoh:
Review and future prospects of low-voltage RAM circuits. IBM J. Res. Dev. 47(5-6): 525-552 (2003)
1990 – 1999
- 1995
- [j7]Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda:
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits 30(11): 1165-1173 (1995) - [j6]Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki:
Low-noise, high-speed data transmission using a ringing-canceling output buffer. IEEE J. Solid State Circuits 30(12): 1569-1574 (1995) - 1994
- [j5]Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki:
A charge recycle refresh for Gb-scale DRAM's in file applications. IEEE J. Solid State Circuits 29(6): 715-722 (1994) - [j4]Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Subthreshold-current reduction circuits for multi-gigabit DRAM's. IEEE J. Solid State Circuits 29(7): 761-769 (1994) - [j3]Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. IEEE J. Solid State Circuits 29(8): 887-894 (1994)
1980 – 1989
- 1989
- [j2]Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh:
New DRAM noise generation under half-Vcc precharge and its reduction using a transposed amplifier. IEEE J. Solid State Circuits 24(4): 889-894 (1989) - 1988
- [j1]Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi:
An experimental large-capacity semiconductor file memory using 16-levels/cell storage. IEEE J. Solid State Circuits 23(1): 27-33 (1988)
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