"Device-conscious circuit designs for 0.5-V high-speed memory-rich ..."

Akira Kotabe et al. (2011)

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DOI: 10.1109/CICC.2011.6055313

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-07

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Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi:
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC 2011: 1-7

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