"Word-line architecture for highly reliable 64-Mb DRAM."

Daisaburo Takashima et al. (1992)

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DOI: 10.1109/4.126550

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type: Journal Article

metadata version: 2025-02-03

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Daisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Kazunori Ohuchi:
Word-line architecture for highly reliable 64-Mb DRAM. IEEE J. Solid State Circuits 27(4): 603-609 (1992)

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