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Tomohisa Wada
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2020 – today
- 2023
- [c11]Gennan Hayashi, Yusuke Oshiro, Shiho Oshiro, Tomohisa Wada:
Intelligent Mobile Channel Estimation and Inter Carrier Interference Cancelation for 5G Services in Indian Shinkansen "Bullet Train". CVMI 2023: 1-5 - [c10]Kaisei Matsumoto, Takao Toma, Shiho Oshiro, Tomohisa Wada:
Intelligent Constellation Generation based on Autoencoder Communication System. CVMI 2023: 1-6 - [c9]Yusuke Oshiro, Gennan Hayashi, Shiho Oshiro, Tomohisa Wada:
5G High Speed DRONE Air Logistics Supported by Advanced 5G Mobile Communication System. CVMI 2023: 1-6 - [c8]Seizan Tsugawa, Takao Toma, Shiho Oshiro, Tomohisa Wada:
Scalability in Autoencoder-based OFDM Communication System. CVMI 2023: 1-5
2010 – 2019
- 2019
- [c7]Mehdi Mohammadi, Mursal Dawodi, Tomohisa Wada, Nadira Ahmadi
:
Comparative study of supervised learning algorithms for student performance prediction. ICAIIC 2019: 124-127 - [c6]Tomohisa Wada, Takao Toma, Mursal Dawodi, Jawid Ahmad Baktash:
A Denoising Autoencoder based wireless channel transfer function estimator for OFDM communication system. ICAIIC 2019: 530-533 - 2016
- [c5]Hidemitsu Kiyuna, Rie Saotome, Tran Minh Hai, Atsushi Kinjo, Taisaku Suzuki, Tomohisa Wada:
Comparison of SC-FDM with OFDM in underwater acoustic communication system. ISPACS 2016: 1-5 - 2010
- [j12]Phuong Thi Thu Pham, Tomohisa Wada:
Pilot-Aided Channel Estimation for WiMAX 802.16e Downlink Partial Usage of Subchannel System Using Least Squares Line Fitting. IEICE Trans. Commun. 93-B(6): 1494-1501 (2010) - [j11]Phuong Thi Thu Pham, Tomohisa Wada:
Effective Scheme of Channel Tracking and Estimation for Mobile WiMAX DL-PUSC System. J. Comput. Networks Commun. 2010: 806279:1-806279:9 (2010) - [c4]Jing Gao, Tomohisa Wada:
ISI and ICI Suppression for Mobile OFDM System by Using a Hybrid 2-Layer Diversity Receiver. MOBILWARE 2010: 17-28 - [c3]Zhian Zheng, Dang Hai Pham, Tomohisa Wada:
Applications of Adaptive Belief Propagation Decoding for Long Reed-Solomon Codes. AST/UCMA/ISA/ACN 2010: 150-158 - [c2]Zhian Zheng, Yoshitomo Kaneda, Dang Hai Pham, Tomohisa Wada:
Modified Structures of Viterbi Alogrithm for Forced-State Method in Concatenated Coding System of ISDB-T. AST/UCMA/ISA/ACN 2010: 239-249
2000 – 2009
- 2009
- [j10]Jing Gao, Takashi Iida, Hiroyuki Mizutani, Sadanori Sakaguchi, Shuji Murakami, Atsushi Shimizu, Tomohisa Wada:
The Implementation of a 2/4/8 Antennas Configurable Diversity OFDM Receiver for Mobile HDTV Application. Int. J. Digit. Multim. Broadcast. 2009: 303627:1-303627:9 (2009) - [c1]Phuong Thi Thu Pham, Tomohisa Wada:
Performance Analysis of a Joint Space-Time Block Codes and Channel Estimation Scheme in DL-PUSC Mode of Mobile WiMAX. EuropeComm 2009: 101-112 - 2008
- [j9]Dang Hai Pham, Jing Gao, Takanobu Tabata, Hirokazu Asato, Satoshi Hori, Tomohisa Wada:
Implementation of Joint Pre-FFT Adaptive Array Antenna and Post-FFT Space Diversity Combining for Mobile ISDB-T Receiver. IEICE Trans. Commun. 91-B(1): 127-138 (2008) - 2006
- [j8]Dang Hai Pham, Takanobu Tabata, Hirokazu Asato, Satoshi Hori, Tomohisa Wada:
Joint Hardware-Software Implementation of Adaptive Array Antenna for ISDB-T Reception. IEICE Trans. Commun. 89-B(12): 3215-3224 (2006)
1990 – 1999
- 1999
- [j7]Hirotoshi Sato, Tomohisa Wada, Shigeki Ohbayashi, Kunihiko Kozaru, Yasuyuki Okamoto, Yoshiko Higashide, Tadayuki Shimizu, Yukio Maki, Rui Morimoto, Hisakazu Otoi, Tsuyoshi Koga, Hiroki Honda, Makoto Taniguchi, Yutaka Arita, Toru Shiomi:
A 500-MHz pipelined burst SRAM with improved SER immunity. IEEE J. Solid State Circuits 34(11): 1571-1579 (1999) - 1998
- [j6]Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada:
A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. IEEE J. Solid State Circuits 33(11): 1672-1681 (1998) - 1993
- [j5]Toru Shiomi, Tomohisa Wada, Shigeki Ohbayashi, Atsushi Ohba, Hiroki Honda, Yoshiyuki Ishigaki, Shiro Hine, Kenji Anami, Kimio Suzuki, Tadashi Sumi:
A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture. IEEE J. Solid State Circuits 28(12): 1362-1369 (1993) - 1992
- [j4]Tomohisa Wada, Suresh Rajan, Steven A. Przybylski:
An analytical access time model for on-chip cache memories. IEEE J. Solid State Circuits 27(8): 1147-1156 (1992) - 1991
- [j3]Tomohisa Wada, Masanao Eino, Motomu Ukita, Kenji Anami:
Variable bit organization as a new test function for standard memories. IEEE J. Solid State Circuits 26(1): 51-54 (1991) - [j2]Hirotada Kuriyama, Toshihiko Hirose, Shuji Murakami, Tomohisa Wada, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami:
An 8 ns 4 Mb serial access memory. IEEE J. Solid State Circuits 26(4): 502-506 (1991) - 1990
- [j1]Tomohisa Wada, Masanao Eino, Kenji Anami:
Simple noise model and low-noise data-output buffer for ultrahigh-speed memories. IEEE J. Solid State Circuits 25(6): 1586-1588 (1990)
Coauthor Index

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