"A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line ..."

Hirotoshi Sato et al. (1998)

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DOI: 10.1109/4.726557

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type: Journal Article

metadata version: 2022-07-05

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Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada:
A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. IEEE J. Solid State Circuits 33(11): 1672-1681 (1998)

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