"An analytical access time model for on-chip cache memories."

Tomohisa Wada, Suresh Rajan, Steven A. Przybylski (1992)

> Home

Details and statistics

DOI: 10.1109/4.148323

access: closed

type: Journal Article

metadata version: 2025-02-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/WadaRP92
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/WadaRP92
Tomohisa Wada, Suresh Rajan, Steven A. Przybylski:
An analytical access time model for on-chip cache memories. IEEE J. Solid State Circuits 27(8): 1147-1156 (1992)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.