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2020 – today
- 2024
[j26]P. V. Ananda Mohan:
New Generalized Impedance Converter (GIC)-Based Two-Opamp Active RC Biquads. Circuits Syst. Signal Process. 43(3): 1366-1390 (2024)- 2023
- [j25]P. V. Ananda Mohan:
Analysis of GIC-Based Frequency-Dependent Negative Resistance-Based Filters. Circuits Syst. Signal Process. 42(4): 2433-2451 (2023) - [c9]P. V. Ananda Mohan:
Hash-based Digital Signatures- A tutorial review. PKIA 2023: 1-8 - 2022
- [c8]P. V. Ananda Mohan, Abey Jacob, Raghavendra S. Patil:
Public Key Cryptographic Implementation Validation: A Review. PKIA 2022: 1-8 - 2021
- [j24]P. V. Ananda Mohan
, P. S. Phalguna:
Evaluation of Mixed-Radix Digit Computation Techniques for the Three Moduli RNS {2n-1, 2n, 2n+1-1}. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1418-1422 (2021) - 2020
- [j23]P. V. Ananda Mohan:
On Actively Compensated Amplifiers Using Negative Impedance Converters. IEEE Trans. Circuits Syst. II Express Briefs 67-II(4): 640-644 (2020)
2010 – 2019
- 2018
- [j22]P. V. Ananda Mohan:
Reverse Converters for the Moduli Set { \(2^{n}, 2^{n-1}-1, 2^{n}-1, 2^{n+1}-1\}(n\, \hbox {Even})\). Circuits Syst. Signal Process. 37(8): 3605-3634 (2018) - [j21]P. S. Phalguna, Dattaguru V. Kamat, P. V. Ananda Mohan:
RNS-to-Binary Converters for New Three-Moduli Sets {2k-3, 2k-2, 2k-1} and {2k+1, 2k+2, 2k+3}. J. Circuits Syst. Comput. 27(14): 1850224:1-1850224:20 (2018) - [c7]P. S. Phalguna, Dattaguru V. Kamat, P. V. Ananda Mohan:
New Reverse converters for the four-moduli set {2n, 2n-1, 2n+1, 2n-1-1} for n even. MWSCAS 2018: 416-419 - 2017
- [j20]P. V. Ananda Mohan:
Reverse Conversion Using Core Function, CRT and Mixed Radix Conversion. Circuits Syst. Signal Process. 36(7): 2847-2874 (2017) - 2016
- [j19]P. V. Ananda Mohan:
RNS to Binary Conversion Using Diagonal Function and Pirlo and Impedovo Monotonic Function. Circuits Syst. Signal Process. 35(3): 1063-1076 (2016) - 2015
- [j18]P. V. Ananda Mohan, Yaohua Zhao, Pui-In Mak, Rui Paulo Martins, Franco Maloberti:
Corrections to "A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad". IEEE J. Solid State Circuits 50(10): 2464 (2015) - 2014
- [j17]Rashmi R. Rachh, P. V. Ananda Mohan, Basavaraj S. Anami:
Implementation of AES Key Schedule Using Look-Ahead Technique. Circuits Syst. Signal Process. 33(11): 3663-3670 (2014) - [j16]P. V. Ananda Mohan, Eric A. M. Klumperink, Dlovan H. Mahrof, Bram Nauta:
Comments on "Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity". IEEE J. Solid State Circuits 49(9): 2083 (2014) - 2013
- [j15]P. V. Ananda Mohan:
Comments on "Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors". IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2235-2236 (2013) - 2012
- [j14]Rashmi R. Rachh, P. V. Ananda Mohan, Basavaraj S. Anami:
Efficient Implementations for AES Encryption and Decryption. Circuits Syst. Signal Process. 31(5): 1765-1785 (2012) - 2011
- [j13]Dattaguru V. Kamat, Pemmaraju V. Ananda Mohan, K. Gopalakrishna Prabhu:
Active-RC filters using two-stage OTAs with and without feed-forward compensation. IET Circuits Devices Syst. 5(6): 527-535 (2011) - [j12]P. V. Ananda Mohan:
Comments on "Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers". IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2114-2116 (2011) - 2010
- [j11]Dattaguru V. Kamat, P. V. Ananda Mohan, K. Gopalakrishna Prabhu:
Novel First-Order and Second-Order Current-Mode Filters Using Multiple-Output Operational Transconductance Amplifiers. Circuits Syst. Signal Process. 29(3): 553-576 (2010) - [j10]P. V. Ananda Mohan:
Sensitivity Analysis of Third and Fourth-Order Filters. Circuits Syst. Signal Process. 29(5): 999-1005 (2010) - [j9]Dattaguru V. Kamat, Pemmaraju V. Ananda Mohan, K. Gopalakrishna Prabhu:
Current-mode operational transconductance amplifier-capacitor biquad filter structures based on Tarmy-Ghausi Active-RC filter and second-order digital all-pass filters. IET Circuits Devices Syst. 4(4): 346-364 (2010)
2000 – 2009
- 2008
- [c6]Rashmi Ramesh Racch, Pemmaraju V. Ananda Mohan:
Implementation of AES S-Boxes using combinational logic. ISCAS 2008: 3294-3297 - 2007
- [j8]P. V. Ananda Mohan:
Comments on "A 4th-Order Active- Gm-RC Reconfigurable (UMTS/WLAN) Filter". IEEE J. Solid State Circuits 42(2): 457-458 (2007) - [j7]Pemmaraju V. Ananda Mohan, A. Benjamin Premkumar:
RNS-to-Binary Converters for Two Four-Moduli Sets {2n-1, 2n, 2n+1, 2n+1-1} and {2n-1, 2n, 2n+1, 2n+1+1}. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(6): 1245-1254 (2007) - [j6]Pemmaraju V. Ananda Mohan:
RNS-To-Binary Converter for a New Three-Moduli Set {2n+1-1, 2n, 2n-1}. IEEE Trans. Circuits Syst. II Express Briefs 54-II(9): 775-779 (2007) - 2005
- [j5]P. V. Ananda Mohan:
Floating Capacitance Simulation Using Current Conveyors. J. Circuits Syst. Comput. 14(1): 123-128 (2005) - 2003
- [c5]P. V. Ananda Mohan:
Fast implementations of Montgomery's modular multiplication algorithm. ISCAS (4) 2003: 125-128
1990 – 1999
- 1999
- [j4]P. V. Ananda Mohan:
Efficient Design of Binary to RNS Converters. J. Circuits Syst. Comput. 9(3-4): 145-154 (1999) - 1996
- [c4]D. V. Poornaiah, P. V. Ananda Mohan:
A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. VLSI Design 1996: 69-72 - 1995
- [j3]P. V. Ananda Mohan:
Capacitor Floatation Scheme using only OTAs and Grounded capacitors. J. Circuits Syst. Comput. 5(2): 181-198 (1995) - [c3]D. V. Poornaiah, P. V. Ananda Mohan:
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. VLSI Design 1995: 392-397 - 1994
- [c2]P. V. Ananda Mohan:
Novel Design for Binary to RNS Converters. ISCAS 1994: 357-360 - 1993
- [c1]Y. V. Ramana Rao, P. V. Ananda Mohan:
Novel oversampled A/D converters based on error spectrum shaping. ISCAS 1993: 212-215
1980 – 1989
- 1987
- [j2]P. V. Ananda Mohan:
New structures for MOSFET-C filters. Proc. IEEE 75(7): 957-960 (1987) - 1985
- [j1]P. V. Ananda Mohan:
Active filter design using cascaded identical low-order (≥ 2) filter sections. Proc. IEEE 73(10): 1525-1526 (1985)
Coauthor Index
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