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ORCIDKenichi Imamiya
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2000 – 2009
- 2008
[j6]Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, Kiyoaki Iwasa, Michio Nakagawa, Masaki Fujiu, Takahiro Shimizu, Mitsuaki Honma, Satoru Hoshi, Toshimasa Kawaai, Kazunori Kanebako, Susumu Yoshikawa, Hideyuki Tabata, Atsushi Inoue, Toshiyuki Takahashi, Toshifumi Shano, Yukio Komatsu, Katsushi Nagaba, Mitsuhiko Kosakai, Noriaki Motohashi, Kazuhisa Kanazawa, Kenichi Imamiya, Hiroto Nakai, Menahem Lasser, Mark Murin, Avraham Meir, Arik Eyal, Mark Shlick:
A 70 nm 16 Gb 16-Level-Cell NAND flash Memory. IEEE J. Solid State Circuits 43(4): 929-937 (2008)- 2002
- [j5]Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che:
A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed. IEEE J. Solid State Circuits 37(11): 1493-1501 (2002) - 2000
- [j4]Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui:
A source-line programming scheme for low-voltage operation NAND flash memories. IEEE J. Solid State Circuits 35(5): 672-681 (2000)
1990 – 1999
- 1999
- [j3]Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui:
A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories. IEEE J. Solid State Circuits 34(5): 675-684 (1999) - [j2]Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui:
A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology. IEEE J. Solid State Circuits 34(11): 1536-1543 (1999) - 1995
- [j1]Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto:
A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. IEEE J. Solid State Circuits 30(11): 1157-1164 (1995)
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